ST STM32L4x6 Reference Manual page 1477

RM0351
Bit 3 FULL1
Bit 2 Reserved, must be kept at reset value.
Bits 1:0 FMP1[1:0]
CAN interrupt enable register (CAN_IER)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
ERRIE Res. Res. Res.
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Bits 31:18 Reserved, must be kept at reset value.
Bit 17 SLKIE
Bit 16 WKUIE
Bit 15 ERRIE
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 LECIE
Bit 10 BOFIE
Bit 9 EPVIE
:
FIFO 1 full
Set by hardware when three messages are stored in the FIFO.
This bit is cleared by software.
:
FIFO 1 message pending
These bits indicate how many messages are pending in the receive FIFO1.
FMP1 is increased each time the hardware stores a new message in to the FIFO1. FMP is
decreased each time the software releases the output mailbox by setting the RFOM1 bit.
28 27 26 25
Res. Res. Res.
12 11 10 9
LEC BOF EPV
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:
Sleep interrupt enable
0: No interrupt when SLAKI bit is set.
1: Interrupt generated when SLAKI bit is set.
:
Wakeup interrupt enable
0: No interrupt when WKUI is set.
1: Interrupt generated when WKUI bit is set.
:
Error interrupt enable
0: No interrupt will be generated when an error condition is pending in the CAN_ESR.
1: An interrupt will be generation when an error condition is pending in the CAN_ESR.
:
Last error code interrupt enable
0: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on error
detection.
1: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error detection.
:
Bus-off interrupt enable
0: ERRI bit will not be set when BOFF is set.
1: ERRI bit will be set when BOFF is set.
:
Error passive interrupt enable
0: ERRI bit will not be set when EPVF is set.
1: ERRI bit will be set when EPVF is set.
24 23 22
Res. Res. Res.
8 7 6
EWG FOV
Res.
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DocID024597 Rev 3
Controller area network (bxCAN)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
FF FMP FOV FF
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17 16
SLKIE WKUIE
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1 0
FMP TME
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