ST STM32L4x6 Reference Manual page 1577

RM0351
43.15.45 OTG device endpoint-x control register (OTG_DOEPCTLx)
(x = 1..5 , where x = Endpoint_number)
Address offset for OUT endpoints: 0xB00 + (Endpoint_number × 0x20)
Reset value: 0x0000 0000
The application uses this register to control the behavior of each logical endpoint other than
endpoint 0.
31 30 29
SD1 SD0
PID/ PID/
EPENA EPDIS
SODD SEVN
FRM FRM
rs rs w
15 14 13
USBA
Res. Res. Res.
EP
rw
Bit 31 EPENA: Endpoint enable
– SETUP phase done
– Endpoint disabled
– Transfer completed
Bit 30 EPDIS: Endpoint disable
Bit 29 SD1PID: Set DATA1 PID
SODDFRM: Set odd frame
Bit 28 SD0PID: Set DATA0 PID
SEVNFRM: Set even frame
Bit 27 SNAK: Set NAK
28 27 26 25
SNAK CNAK Res.
w w w
12 11 10 9
Res.
rw rw
Applies to IN and OUT endpoints.
The application sets this bit to start transmitting data on an endpoint.
The core clears this bit before setting any of the following interrupts on this endpoint:
The application sets this bit to stop transmitting/receiving data on an endpoint, even before
the transfer for that endpoint is complete. The application must wait for the Endpoint
disabled interrupt before treating the endpoint as disabled. The core clears this bit before
setting the Endpoint disabled interrupt. The application must set this bit only if Endpoint
enable is already set for this endpoint.
Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the endpoint
data PID (DPID) field in this register to DATA1.
Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd
frame (EONUM) field to odd frame.
Applies to interrupt/bulk OUT endpoints only.
Writing to this field sets the endpoint data PID (DPID) field in this register to DATA0.
Applies to isochronous OUT endpoints only.
Writing to this field sets the Even/Odd frame (EONUM) field to even frame.
A write to this bit sets the NAK bit for the endpoint.
Using this bit, the application can control the transmission of NAK handshakes on an
endpoint. The core can also set this bit for OUT endpoints on a Transfer Completed
interrupt, or after a SETUP is received on the endpoint.
24 23 22
Res. Res. Res.
8 7 6
rw rw rw
DocID024597 Rev 3
USB on-the-go full-speed (OTG_FS)
21 20 19 18
STALL SNPM EPTYP
rw/rs rw rw rw
5 4 3
MPSIZ
rw rw rw rw
17 16
EO
NAK
NUM/
STS
DPID
r r
2 1 0
rw rw
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