ST STM32L4x6 Reference Manual page 1479

RM0351
Bits 31:24 REC[7:0]
Bits 23:16 TEC[7:0]
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:4 LEC[2:0]
Bit 3 Reserved, must be kept at reset value.
Bit 2 BOFF
Bit 1 EPVF: Error passive flag
Bit 0 EWGF
CAN bit timing register (CAN_BTR)
Address offset: 0x1C
Reset value: 0x0123 0000
This register can only be accessed by the software when the CAN hardware is in
initialization mode.
31 30 29
SILM LBKM Res.
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15 14 13
Res. Res. Res.
:
Receive error counter
The implementing part of the fault confinement mechanism of the CAN protocol. In case of
an error during reception, this counter is incremented by 1 or by 8 depending on the error
condition as defined by the CAN standard. After every successful reception the counter is
decremented by 1 or reset to 120 if its value was higher than 128. When the counter value
exceeds 127, the CAN controller enters the error passive state.
:
Least significant byte of the 9-bit transmit error counter
The implementing part of the fault confinement mechanism of the CAN protocol.
:
Last error code
This field is set by hardware and holds a code which indicates the error condition of the last
error detected on the CAN bus. If a message has been transferred (reception or
transmission) without error, this field will be cleared to '0'.
The LEC[2:0] bits can be set to value 0b111 by software. They are updated by hardware to
indicate the current communication status.
000: No Error
001: Stuff Error
010: Form Error
011: Acknowledgment Error
100: Bit recessive Error
101: Bit dominant Error
110: CRC Error
111: Set by software
:
Bus-off flag
This bit is set by hardware when it enters the bus-off state. The bus-off state is entered on
TEC overflow, greater than 255, refer to
This bit is set by hardware when the Error Passive limit has been reached (Receive Error
Counter or Transmit Error Counter>127).
:
Error warning flag
This bit is set by hardware when the warning limit has been reached
(Receive Error Counter or Transmit Error Counter≥96).
28 27 26 25
Res. Res. Res. SJW[1:0]
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12 11 10 9
Res. Res. Res.
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Section 42.7.6 on page
24 23 22
Res.
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8 7 6
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DocID024597 Rev 3
Controller area network (bxCAN)
1466.
21 20 19
TS2[2:0]
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5 4 3
BRP[9:0]
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18 17 16
TS1[3:0]
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2 1 0
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