ST STM32L4x6 Reference Manual page 1569

RM0351
are used. Bits in this register are set and cleared when the application sets and clears bits in
the corresponding Device Endpoint-x interrupt register (OTG_DIEPINTx/OTG_DOEPINTx).
31 30 29
r r r
15 14 13
r r r
Bits 31:16 OEPINT: OUT endpoint interrupt bits
Bits 15:0 IEPINT: IN endpoint interrupt bits
43.15.38 OTG all endpoints interrupt mask register
(OTG_DAINTMSK)
Address offset: 0x81C
Reset value: 0x0000 0000
The OTG_DAINTMSK register works with the Device endpoint interrupt register to interrupt
the application when an event occurs on a device endpoint. However, the OTG_DAINT
register bit corresponding to that interrupt is still set.
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:16 OEPM: OUT EP interrupt mask bits
Bits 15:0 IEPM: IN EP interrupt mask bits
28 27 26 25
r r r r
12 11 10 9
r r r r
One bit per OUT endpoint:
Bit 16 for OUT endpoint 0, bit 18 for OUT endpoint 3.
One bit per IN endpoint:
Bit 0 for IN endpoint 0, bit 3 for endpoint 3.
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
One per OUT endpoint:
Bit 16 for OUT EP 0, bit 18 for OUT EP 3
0: Masked interrupt
1: Unmasked interrupt
One bit per IN endpoint:
Bit 0 for IN EP 0, bit 3 for IN EP 3
0: Masked interrupt
1: Unmasked interrupt
DocID024597 Rev 3
USB on-the-go full-speed (OTG_FS)
24 23 22 21
OEPINT
r r r r
8 7 6 5
IEPINT
r r r r
24 23 22 21
OEPM
rw rw rw rw
8 7 6 5
IEPM
rw rw rw rw
20 19 18 17
r r r r
4 3 2 1
r r r r
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
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16
r
0
r
16
rw
0
rw
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