ST STM32L4x6 Reference Manual page 1529

RM0351
31 30 29
AHB
Res. Res. Res.
IDL
r
15 14 13
Res. Res. Res. Res.
Bit 31 AHBIDL: AHB master idle
Indicates that the AHB master state machine is in the Idle condition.
Note: Accessible in both device and host modes.
Bits 30:11 Reserved, must be kept at reset value for USB OTG FS
Bits 10:6 TXFNUM: Tx FIFO number
This is the FIFO number that must be flushed using the Tx FIFO Flush bit. This field must not
be changed until the core clears the Tx FIFO Flush bit.
00000:
00001:
00010: Tx FIFO 2 flush in device mode
...
01111: Tx FIFO 15 flush in device mode
10000: Flush all the transmit FIFOs in device or host mode.
Note: Accessible in both device and host modes.
Bit 5 TXFFLSH: Tx FIFO flush
This bit selectively flushes a single or all transmit FIFOs, but cannot do so if the core is in the
midst of a transaction.
The application must write this bit only after checking that the core is neither writing to the Tx
FIFO nor reading from the Tx FIFO. Verify using these registers:
Read—NAK Effective Interrupt ensures the core is not reading from the FIFO
Write—AHBIDL bit in OTG_GRSTCTL ensures the core is not writing anything to the FIFO.
Flushing is normally recommended when FIFOs are reconfigured. FIFO flushing is also
recommended during device endpoint disable. The application must wait until the core clears
this bit before performing any operations. This bit takes eight clocks to clear, using the slower
clock of phy_clk or hclk.
Note: Accessible in both device and host modes.
Bit 4 RXFFLSH: Rx FIFO flush
The application can flush the entire Rx FIFO using this bit, but must first ensure that the core
is not in the middle of a transaction.
The application must only write to this bit after checking that the core is neither reading from
the Rx FIFO nor writing to the Rx FIFO.
The application must wait until the bit is cleared before performing any other operations. This
bit requires 8 clocks (slowest of PHY or AHB clock) to clear.
Note: Accessible in both device and host modes.
Bit 3 Reserved, must be kept at reset value.
28 27 26 25
Res. Res. Res.
12 11 10 9
Res.
– Non-periodic Tx FIFO flush in host mode
– Tx FIFO 0 flush in device mode
– Periodic Tx FIFO flush in host mode
– Tx FIFO 1 flush in device mode
DocID024597 Rev 3
USB on-the-go full-speed (OTG_FS)
24 23 22
Res. Res. Res. Res.
8 7 6
TXF
TXFNUM
FLSH
rw
21 20 19 18
Res. Res. Res.
5 4 3 2
RXF
Res. FCRST
FLSH
rs rs rs
17 16
Res. Res.
1 0
Res. CSRST
rs
1529/1693
1644