ST STM32L4x6 Reference Manual page 1527

RM0351
Reset value: 0x0000 1440
This register can be used to configure the core after power-on or a changing to host mode
or device mode. It contains USB and USB-PHY related configuration parameters. The
application must program this register before starting any transactions on either the AHB or
the USB. Do not make changes to this register after the initial programming.
31 30 29
FD FH
Res. Res.
MOD MOD
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15 14 13
Res. Res.
Bit 31 Reserved, must be kept at reset value.
Bit 30 FDMOD: Force device mode
Writing a 1 to this bit, forces the core to device mode irrespective of the OTG_ID input pin.
0: Normal mode
1: Force device mode
After setting the force bit, the application must wait at least 25 ms before the change takes
effect.
Note: Accessible in both device and host modes.
Bit 29 FHMOD: Force host mode
Writing a 1 to this bit, forces the core to host mode irrespective of the OTG_ID input pin.
0: Normal mode
1: Force host mode
After setting the force bit, the application must wait at least 25 ms before the change takes
effect.
Note: Accessible in both device and host modes.
Bits 28:24 Reserved, must be kept at reset value.
Bits 25:15 Reserved, must be kept at reset value for USB OTG FS
Bit 14 Reserved, must be kept at reset value.
Bits 13:10 TRDT: USB turnaround time
These bits allows to set the turnaround time in PHY clocks. They must be configured
according to
TRDT values allow stretching the USB response time to IN tokens in order to compensate for
longer AHB read access latency to the Data FIFO.
Note: Only accessible in device mode.
Bit 9 HNPCAP: HNP-capable
The application uses this bit to control the
0: HNP capability is not enabled.
1: HNP capability is enabled.
Note: Accessible in both device and host modes.
28 27 26 25
Res. Res. Res.
12 11 10 9
HNP
TRDT
CAP
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Table 261: TRDT
DocID024597 Rev 3
USB on-the-go full-speed (OTG_FS)
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
SRP PHY
Res. Res.
CAP SEL
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values, depending on the application AHB frequency. Higher
OTG_FS
20 19 18
Res. Res. Res.
4 3 2
Res. Res.
controller's HNP capabilities.
17 16
Res. Res.
1 0
TOCAL
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