ST STM32L4x6 Reference Manual page 1490

Controller area network (bxCAN)
Filter bank i register x (CAN_FiRx) (i = 0..13, x = 1, 2)
Address offsets: 0x240 to 0x2AC
Reset value: 0xXXXX XXXX
There are 14 filter banks, i= 0 to 13. Each filter bank i is composed of two 32-bit registers,
CAN_FiR[2:1].
This register can only be modified when the FACTx bit of the CAN_FAxR register is cleared
or when the FINIT bit of the CAN_FMR register is set.
31 30 29
FB31 FB30 FB29 FB28
rw rw rw
15 14 13
FB15 FB14 FB13 FB12
rw rw rw
In all configurations:
Bits 31:0 FB[31:0]: Filter bits
Identifier
Each bit of the register specifies the level of the corresponding bit of the expected identifier.
0: Dominant bit is expected
1: Recessive bit is expected
Mask
Each bit of the register specifies whether the bit of the associated identifier register must
match with the corresponding bit of the expected identifier or not.
0: Don't care, the bit is not used for the comparison
1: Must match, the bit of the incoming identifier must have the same level has specified in
the corresponding identifier register of the filter.
Note: Depending on the scale and mode configuration of the filter the function of each register can
differ. For the filter mapping, functions description and mask registers association, refer to
Section 42.7.4: Identifier filtering on page
A Mask/Identifier register in mask mode has the same bit mapping as in identifier list
mode.
For the register mapping/addresses of the filter banks please refer to the
page 1491.
1490/1693
28 27 26 25
FB27 FB26 FB25
rw rw rw rw
12 11 10 9
FB11 FB10 FB9
rw rw rw rw
DocID024597 Rev 3
24 23 22 21
FB24 FB23 FB22 FB21
rw rw rw rw
8 7 6 5
FB8 FB7 FB6 FB5
rw rw rw rw
1460.
20 19 18 17
FB20 FB19 FB18 FB17
rw rw rw rw
4 3 2 1
FB4 FB3 FB2 FB1
rw rw rw rw
Table 254 on
RM0351
16
FB16
rw
0
FB0
rw