ST STM32L4x6 Reference Manual page 1561

RM0351
43.15.29 OTG Host channel-x interrupt mask register (OTG_HCINTMSKx)
(x = 0..11, where x = Channel_number)
Address offset: 0x50C + (Channel_number × 0x20)
Reset value: 0x0000 0000
This register reflects the mask for each channel status described in the previous section.
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:11 Reserved, must be kept at reset value.
Bit 10 DTERRM: Data toggle error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 9 FRMORM: Frame overrun mask
0: Masked interrupt
1: Unmasked interrupt
Bit 8 BBERRM: Babble error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 7 TXERRM: Transaction error mask
0: Masked interrupt
1: Unmasked interrupt
Bit 6 Reserved, must be kept at reset value for USB OTG FS.
Bit 5 ACKM: ACK response received/transmitted interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 4 NAKM: NAK response received interrupt mask
0: Masked interrupt
1: Unmasked interrupt
Bit 3 STALLM: STALL response received interrupt mask
0: Masked interrupt
1: Unmasked interrupt
28 27 26 25
Res. Res. Res.
12 11 10 9
DTERR FRM
Res.
M ORM
rw rw
DocID024597 Rev 3
USB on-the-go full-speed (OTG_FS)
24 23 22
Res. Res. Res. Res.
8 7 6
BBERR TXERR
Res. ACKM
M M
rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
STALL
NAKM Res.
M
rw rw rw
17 16
Res. Res.
1 0
XFRC
CHHM
M
rw rw
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