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• Direct transition from the subactive mode to the active mode
When a SLEEP instruction is executed in the subactive mode while the DTON bit in SYSCR2
is set to 1 and the LSON bit in SYSCR2 is cleared to 0, a direct transition is made from the
subactive mode to the active mode. The time from the start of SLEEP instruction execution to
the end of interrupt exception handling (the direct transition time) is calculated by equation (2).
Direct transition time = {(number of SLEEP instruction execution states) + (number of internal
processing states)} × (tsubcyc before transition) + {(waiting time set in bits STS2 to STS0) +
(number of interrupt exception handling states)} × (tcyc after transition)...................... (2)
[Example]
Direct transition time = (2 + 1) × 8tw + (8192 + 14) × tosc = 24tw + 8206tosc
(when the CPU operating clock of øw/8 → øosc and a waiting time of 8192 states are selected)
<Symbols>
tosc: OSC clock cycle time
tw: watch clock cycle time
tcyc: system clock (ø) cycle time
tsubcyc: subclock (øSUB) cycle time
6.10
Module Standby Mode
The module standby mode can be set to any peripheral module. In the module standby mode, the
clock supply to modules and the module functions stop much like the states in the standby mode.
Therefore, power consumption can be reduced.
The module standby mode can be specified by setting each bit of module standby control register
1 (MSTCR1) to 1. The module standby mode can be canceled by clearing each bit of module
standby control register 1 (MSTCR1) to 0.
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