Burst Operation - Hitachi H8S/2678 Series Reference Manual

16-bit single-chip microcomputer

Table of Contents

H8S/2678 Series chip

(Address shift size

set to 10 bits)

Burst Operation

With DRAM, in addition to full access (normal access) in which data is accessed by outputting a

row address for each access, a fast page mode is also provided which can be used when making

consecutive accesses to the same row address. This mode enables fast (burst) access of data by

simply changing the column address after the row address has been output. Burst access can be

selected by setting the BE bit to 1 in DRAMCR.

Burst Access (Fast Page Mode) Operation Timing: Figures 4.29 and 4.30 show the operation

timing for burst access. When there are consecutive access cycles for DRAM space, the CAS

signal and column address output cycles (two states) continue as long as the row address is the

same for consecutive access cycles. The row address used for the comparison is set with bits

MXC2 to MXC0 in DRAMCR.

Figure 4.28 Example of 2-CAS DRAM Connection

2-CAS type 16-Mbit DRAM

1-Mbyte × 16-bit configuration

10-bit column address

Row address input:

Column address input: