Burst Read - Hitachi SH7095 Hardware User Manual

Table 7.4 SZ and AMX Bits and Address Multiplex Output
Setting
SZ AMX2 AMX1 AMX0
1 0 0
1 0 0
1 0 1
1 0 1
1 1 1
0 0 0
0 0 1
0 1 1
AMX2–AMX0 settings of 100, 101 and 110 are reserved, so do not use them. When SZ = 0, the
settings 001 and 010 are reserved as well, so do not use them either.
Notes: 1. L/H is a bit used to specify commands. It is fixed to L or H by the access mode.
2. Specifies bank address.
7.5.3

Burst Read

Figure 7.15 shows the timing chart for burst reads. In the following example, 2 synchronous
DRAMs of 256k × 16 bits are connected, the data width is 32 bits and the burst length is 4. After a
Tr cycle that performs the ACTV command output, a READA command is called in the Tc cycle
and read data is accepted at internal clock falls from Td1 to Td4. Tap is a cycle for waiting for the
completion of the auto precharge based on the READA command within the synchronous DRAM.
During this period, no new access commands are issued to the same bank. Accesses of the other
bank of the synchronous DRAM by another CS space are possible. Depending on the TRP
specification in the MCR, the SH7095 determines the number of Tap cycles and does not issue a
command to the same bank during that period.
148 Hitachi
Output Timing
0 Column address
Row address
1 Column address
Row address
0 Column address
Row address
1 Column address
Row address
1 Column address
Row address
0 Column address
Row address
1 Column address
Row address
1 Column address
Row address
External Address Pin
A1–A8 A9 A10
A1–A8 A9 A10
A9–A16 A17 A18
A1–A8 A9 A10
A10– A18 A19
A17
A1–A8 A9 A10
A11– A19 A20
A18
A1–A8 A9 L/H
A9–A16 A17 A18
A1–A8 A9 L/H
A9–A16 A17 A17
A1–A8 A9 A10
A9–A16 A17 A18
*1
A1–A8 L/H A18
A9–A16 A17 A18
*1
A1–A8 L/H A17
A9–A16 A16 A17
A11 A12 A13
*1
A11 L/H A21
A19 A20 A21
*1
A11 L/H A22
A20 A21 A22
*1
A11 L/H A23
A21 A22 A23
*1 *2
A19 A12 A13
*2
A19 A20 A21
*1 *2
A18 A12 A13
*2
A18 A20 A21
*1 *2
L/H A20 A13
*2
A19 A20 A21
*2
A11 A12 A13
*2
A19 A20 A21
*2
A11 A12 A13
*2
A19 A20 A21
*2
*2
*2
*2
*2
*2