Dram Control Register A (Drcra) - Hitachi H8/3006 Hardware Manual

Bit 7
CS7E
Initial value 0
Read/Write R/W
CSCR is initialized to H'0F by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Chip Select 7 to 4 Enable (CS7E to CS4E): These bits enable or disable output of
the corresponding chip select signal.
Bit n
CSnE Description
0 Output of chip select signal CSn is disabled
1 Output of chip select signal CSn is enabled
Note: n = 7 to 4
Bits 3 to 0—Reserved: These bits cannot be modified and are always read as 1.
6.2.7

DRAM Control Register A (DRCRA)

Bit 7
DRAS2
Initial value 0
Read/Write R/W
DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface
function, and the access mode, and enables or disables self-refreshing and refresh pin output.
DRCRA is initialized to H'10 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 5—DRAM Area Select (DRAS2 to DRAS0): These bits select which of areas 2 to 5 are
to function as DRAM interface areas (DRAM space), and at the same time select the RAS output
pin corresponding to each DRAM space.
6 5
CS6E CS5E CS4E
0 0
R/W R/W
Chip select 7 to 4 enable
These bits enable or disable
chip select signal output
6 5
DRAS1 DRAS0
0 0
R/W R/W
4 3
— —
0 1
R/W — —
4 3
— BE
1 0
— R/W
2 1 0
— —
1 1 1
— —
Reserved bits
(Initial value)
2 1
RDM SRFMD RFSHE
0 0
R/W R/W
0
0
R/W
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