System Clock Modes - Freescale Semiconductor MCF52277 Reference Manual

Clock Module
7.3.3.1 Loss of Lock Reset Request
The PLL provides the ability to assert reset when a loss-of-lock condition occurs by programming the
PSR[LOLRE] bit. Because the PSR[LOCK, LOCKS] bits are cleared after reset, the reset status register
(RSR) must be read to determine a loss of lock condition occurred. See
Module," for more information on the RSR register. To exit reset in PLL mode, the reference must be
present and the PLL must acquire lock. In PLL bypass mode, the PLL cannot lock; therefore, a loss of lock
condition cannot occur, and LOLRE has no affect.
7.3.3.2 Loss of Lock Interrupt Request
By programming the PSR[LOLIRQ] bit, the PLL provides the ability to request an interrupt when a
loss-of-lock condition occurs. This bit is sticky, and remains asserted until the user clears the
PSR[LOCKS] status bit. LOLIRQ provides information to the lock detect logic to let it know if an interrupt
should be generated upon loss-of-lock. In PLL bypass mode, the PLL cannot lock; therefore, a loss-of-lock
condition cannot occur, and the LOLIRQ has no affect.
7.3.4

System Clock Modes

The system clock source is determined during reset. By default the PLL is placed in crystal-reference mode
and generates a core frequency of 10 times the input clock (internal bus 5x and USB clock 3.75x). The
BOOTMOD pins can override the default mode. See
more information on default configuration, as well as overwriting these defaults during reset.
Table 7-5 shows some of the various clocking scenarios offered on the processor. USB_CLKIN in the USB
OTG column indicates that the USB On-the-Go module receives its clock from the USB_CLKIN signal
rather than the PLL output.
Input Reference/
PCR[PFDR]
Crystal Frequency
f
EXTAL
(User-Defined)
16.67
16
7-10
Table 7-5. MCF52277 Clocking Scenarios (MHz)
OUTDIV1
VCO
(BOOTMOD = 00, 01)
× 30
30 f
EXTAL
Parallel Boot with PLL Enabled
(BOOTMOD = 10 and FB_A19 = 0)
30 500
30 480
MCF52277 Reference Manual, Rev. 1
Chapter 9, "Chip Configuration Module (CCM),"
ColdFire Internal Bus
(Core ÷ 2)
+ 1 Core
Default
× 10
3 f f
EXTAL EXTAL
166.67
3
160
Chapter 11, "Reset Controller
OUTDIV5 USB OTG
1
× 5
8 f
EXTAL
83.33 — USB_CLKIN
80 8
Freescale Semiconductor
for
× 3.75
60