Altera cyclone V Technical Reference page 3085

cv_5v4
2016.10.28
ic_dma_cr
The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit
and receive. This can be programmed regardless of the state of IC_ENABLE.
Module Instance
i2c0
i2c1
i2c2
i2c3
Offset:
0x88
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
ic_dma_cr Fields
Bit
1
tdmae
0
rdmae
I2C Controller
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0xFFC04000
0xFFC05000
0xFFC06000
0xFFC07000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This bit enables/disables the transmit FIFO DMA
channel.
Value
0x0
0x1
This bit enables/disables the receive FIFO DMA
channel.
Value
0x0
0x1
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Reserved
Description
Description
Transmit DMA disable
Transmit DMA enabled
Description
Receive DMA disable
Receive DMA enabled
ic_dma_cr
Register Address
0xFFC04088
0xFFC05088
0xFFC06088
0xFFC07088
21 20 19 18
5 4 3 2
Access
20-67
17 16
1 0
tdmae rdmae
RW RW 0x0
0x0
Reset
RW 0x0
RW 0x0
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