E.1.2 Serial Interface; E.1.3 Scc General Set-Up; E.1.4 Atm - Freescale Semiconductor MPC850 User Manual

MPC850 Overview

E.1.2 Serial Interface

If the time-slot assigner (TSA) is required for routing data to and from the SCC2, the serial
interface RAM entries and clock routing must be set up to run for SCC2 only. Ensure that
SIRAM[CSEL] does not route the time slot to SCC3. See Section 20.2.3.5, "Programming
the SI RAM." Also ensure that the serial interface clock routing invokes proper routing, as
desired, for SCC2 and that bits in the SICR pertaining to SCC3 are cleared. See
Section 20.2.4.3, "SI Clock Route Register (SICR)."

E.1.3 SCC General Set-Up

Although most SCC registers contain configuration bits for two SCCs, ensure that these are
only using SCC2. Refer to Chapter 21, "Serial Communications Controllers." Registers
affected include the GSMR, PSMR, DSR, and TODR. If interrupts are used, ensure that
only SCCE2, SCCM2, SCCS2 are manipulated or observed. See Section 21.4.2, "Handling
SCC Interrupts," which describes SCC event, mask, and status registers.

E.1.4 ATM

The MPC850 does not support ATM or provide a UTOPIA interface. Therefore, Part VI
Asynchronous Transfer Mode does not apply to this device.
Appendix E. MPC850