E.1.1 Unimplemented Signals - Freescale Semiconductor MPC850 User Manual

MPC850 Overview
Embedded Instruction
PowerPC
Core
Load/Store
Baud Rate
Generators
Parallel I/O
Ports
SCC2
TDMa

E.1.1 Unimplemented Signals

The following signals that support SCC3 are not implemented on the MPC850.
• RXD3
• TXD3
• RTS3
• CTS3
• CD3
Note that the alternative functionality of the associated port pins remains available, as
described in Chapter 12, "External Signals."
2-Kbyte
I Cache
Instruction
MMU
Bus
1-Kbyte
D Cache
Data
Bus
MMU
Interrupt Dual-Port
Four
Timers Controller
32-Bit RISC Communications
Processor (CP) and Program ROM
Timer
SCC3 SMC1
Time Slot Assigner
Non-Multiplexed Serial Interface
Figure E-1. MPC850 Block Diagram
MPC850 Family User's Manual
Unified Bus
14 Virtual
RAM
Serial DMA
Channels
and
2 Virtual
IDMA
Channels
Peripheral Bus
SMC2
USB
System Interface Unit
Memory Controller
Bus Interface Unit
System Functions
Real-Time Clock
PCMCIA Interface
Communications
Processor
Module
2
SPI
I C