ST STM32L4+ Series Reference Manual page 1867

RM0432
If the CPHA bit is set, the second edge on the SCK pin captures the first data bit transacted
(falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set). Data are latched on
each occurrence of this clock transition type. If the CPHA bit is reset, the first edge on the
SCK pin captures the first data bit transacted (falling edge if the CPOL bit is set, rising edge
if the CPOL bit is reset). Data are latched on each occurrence of this clock transition type.
The combination of CPOL (clock polarity) and CPHA (clock phase) bits selects the data
capture clock edge.
Figure 537, shows an SPI full-duplex transfer with the four combinations of the CPHA and
CPOL bits.
Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
CPOL = 1
CPOL = 0
NSS (to slave)
Capture strobe
CPOL = 1
CPOL = 0
NSS (to slave)
Capture strobe
1. The order of data bits depends on LSBFIRST bit setting.
Figure 537. Data clock timing diagram
(1)
MOSI MSBit
(1)
MISO
MSBit
(1)
MOSI MSBit
(1)
MISO
MSBit
CPHA =1
CPHA =0
RM0432 Rev 6
Serial peripheral interface (SPI)
LSBit
LSBit
LSBit
LSBit
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