ST STM32L4+ Series Reference Manual page 1859

RM0432
52 Serial peripheral interface (SPI)
52.1 Introduction
The SPI interface can be used to communicate with external devices using the SPI protocol.
SPI mode is selectable by software. SPI Motorola mode is selected by default after a device
reset.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex
synchronous, serial communication with external devices. The interface can be configured
as master and in this case it provides the communication clock (SCK) to the external slave
device. The interface is also capable of operating in multimaster configuration.
52.2 SPI main features
•
Master or slave operation
• Full-duplex synchronous transfers on three lines
•
Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
•
4 to 16-bit data size selection
• Multimaster mode capability
•
8 master mode baud rate prescalers up to f
• Slave mode frequency up to f
•
NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
•
Programmable clock polarity and phase
•
Programmable data order with MSB-first or LSB-first shifting
•
Dedicated transmission and reception flags with interrupt capability
•
SPI bus busy status flag
•
SPI Motorola support
•
Hardware CRC feature for reliable communication:
–
–
• Master mode fault, overrun flags with interrupt capability
•
CRC Error flag
• Two 32-bit embedded Rx and Tx FIFOs with DMA capability
•
Enhanced TI and NSS pulse modes support
52.3 SPI implementation
The following table describes all the SPI instances and their features embedded in the
devices.
CRC value can be transmitted as last byte in Tx mode
Automatic CRC error checking for last received byte
/2
PCLK
/2.
PCLK
RM0432 Rev 6
Serial peripheral interface (SPI)
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