RM0432
NSS
SCK
BSY
MOSI
SPE
TXE
FTLVL
00
MISO
RXNE
DMA or software control at Rx events
FRLVL
DMA Tx TICF
Assumptions for master full-duplex communication example:
•
Data size > 8 bit
If DMA is used:
•
Number of Tx frames transacted by DMA is set to 3
•
Number of Rx frames transacted by DMA is set to 3
See also
and notes.
Figure 540. Master full-duplex communication
MSB
DTx1
3
Enable Tx/Rx DMA or interrupts
DTx2
DTx3
DTx1
10
11
10
4
DRx1
1
00
5
: Communication diagrams on page 1874
2
MSB
DTx2
3
DMA or software control at Tx events
11
10
LSB
DRx2
LSB
DRx1
10
00
10
DMA Rx TICF
for details about common assumptions
RM0432 Rev 6
Serial peripheral interface (SPI)
2
MSB
DTx3
00
DRx3
LSB
DRx2
DRx3
00
10
1
00
MSv19266V2
1875/2301
1893
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