ST STM32L4+ Series Reference Manual page 1860

Serial peripheral interface (SPI)
Table 365. STM32L4Rxxx/STM32L4Sxxx and STM32L4P5xx/STM32L4Q5xx SPI
Enhanced NSSP & TI modes
Hardware CRC calculation
I2S support
Data size configurable
Rx/Tx FIFO size
Wakeup capability from Low-power Sleep
Table 366. STM32L4Rxxx/STM32L4Sxxx and STM32L4P5xx/STM32L4Q5xx SPI
Enhanced NSSP & TI modes
Hardware CRC calculation
I2S support
Data size configurable
Rx/Tx FIFO size
Wakeup capability from Low-power Sleep
52.4 SPI functional description
52.4.1 General description
The SPI allows synchronous, serial communication between the MCU and external devices.
Application software can manage the communication by polling the status flag or using
dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the
following block diagram
1860/2301
SPI features
SPI features
Figure 530.
RM0432 Rev 6
implementation
SPI1
Yes
Yes
No
from 4 to 16-bit
32-bit
Yes
implementation
SPI1
Yes
Yes
No
from 4 to 16-bit
32-bit
Yes
SPI2 SPI3
Yes
Yes
No
from 4 to 16-bit from 4 to 16-bit
32-bit 32-bit
Yes
SPI2 SPI3
Yes
Yes
No
from 4 to 16-bit from 4 to 16-bit
32-bit 32-bit
Yes
RM0432
Yes
Yes
No
Yes
Yes
Yes
No
Yes