ST STM32L4+ Series Reference Manual page 1868

Serial peripheral interface (SPI)
Data frame format
The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the
value of the LSBFIRST bit. The data frame size is chosen by using the DS bits. It can be set
from 4-bit up to 16-bit length and the setting applies for both transmission and reception.
Whatever the selected data frame size, read access to the FIFO must be aligned with the
FRXTH level. When the SPIx_DR register is accessed, data frames are always right-aligned
into either a byte (if the data fits into a byte) or a half-word (see
communication, only bits within the data frame are clocked and transferred.
Figure 538. Data alignment when data length is not equal to 8-bit or 16-bit
DS <= 8 bits: data is right-aligned on byte
Note: The minimum data length is 4 bits. If a data length of less than 4 bits is selected, it is forced
to an 8-bit data frame size.
52.4.7 Configuration of SPI
The configuration procedure is almost the same for master and slave. For specific mode
setups, follow the dedicated sections. When a standard communication is to be initialized,
perform these steps:
1. Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
2. Write to the SPI_CR1 register:
a)
b)
c)
d)
e)
f)
g)
1868/2301
Example: DS = 5 bit
7 5 4 0
XXX Data frame
7
5 4 0
000 Data frame
Configure the serial clock baud rate using the BR[2:0] bits (Note: 4).
Configure the CPOL and CPHA bits combination to define one of the four
relationships between the data transfer and the serial clock (CPHA must be
cleared in NSSP mode). (Note: 2 - except the case when CRC is enabled at TI
mode).
Select simplex or half-duplex mode by configuring RXONLY or BIDIMODE and
BIDIOE (RXONLY and BIDIMODE can't be set at the same time).
Configure the LSBFIRST bit to define the frame format (Note: 2).
Configure the CRCL and CRCEN bits if CRC is needed (while SCK clock signal is
at idle state).
Configure SSM and SSI (Notes: 2 & 3).
Configure the MSTR bit (in multimaster NSS configuration, avoid conflict state on
DS > 8 bits: data is right-aligned on 16 bit
15
TX
15
RX
RM0432 Rev 6
Figure 538). During
Example: DS = 14 bit
14 13 0
XX Data frame
TX
14
13 0
00 Data frame RX
RM0432
MS19589V2