ST STM32L4+ Series Reference Manual page 1862

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Serial peripheral interface (SPI)

Full-duplex communication

By default, the SPI is configured for full-duplex communication. In this configuration, the

shift registers of the master and slave are linked using two unidirectional lines between the

MOSI and the MISO pins. During SPI communication, data is shifted synchronously on the

SCK clock edges provided by the master. The master transmits the data to be sent to the

slave via the MOSI line and receives data from the slave via the MISO line. When the data

frame transfer is complete (all the bits are shifted) the information between the master and

slave is exchanged.

Rx shift register

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the

pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and

slave. For more details see

Half-duplex communication

The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the

SPIx_CR1 register. In this configuration, one single cross connection line is used to link the

shift registers of the master and slave together. During this communication, the data is

synchronously shifted between the shift registers on the SCK clock edge in the transfer

direction selected reciprocally by both master and slave with the BDIOE bit in their

SPIx_CR1 registers. In this configuration, the master's MISO pin and the slave's MOSI pin

are free for other application uses and act as GPIOs.

Rx shift register

Tx shift register

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the

pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and

slave. For more details see

2. In this configuration, the master's MISO pin and the slave's MOSI pin can be used as GPIOs.

3. A critical situation can happen when communication direction is changed not synchronously between two

Figure 531. Full-duplex single master/ single slave application

Tx shift register

Section 52.4.5: Slave select (NSS) pin

Figure 532. Half-duplex single master/ single slave application

Section 52.4.5: Slave select (NSS) pin

RM0432 Rev 6

Tx shift register

Rx shift register

Tx shift register

Rx shift register

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