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Low-power universal asynchronous receiver transmitter (LPUART)
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 TCCF: Transmission complete clear flag
Bit 5 Reserved, must be kept at reset value.
Bit 4 IDLECF: Idle line detected clear flag
Bit 3 ORECF: Overrun error clear flag
Bit 2 NECF: Noise detected clear flag
Bit 1 FECF: Framing error clear flag
Bit 0 PECF: Parity error clear flag
36.7.10
LPUART receive data register (LPUART_RDR)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bits 8:0 RDR[8:0]: Receive data value
36.7.11
LPUART transmit data register (LPUART_TDR)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
1250/1450
Writing 1 to this bit clears the TC flag in the LPUART_ISR register.
Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register.
Writing 1 to this bit clears the ORE flag in the LPUART_ISR register.
Writing 1 to this bit clears the NE flag in the LPUART_ISR register.
Writing 1 to this bit clears the FE flag in the LPUART_ISR register.
Writing 1 to this bit clears the PE flag in the LPUART_ISR register.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see
Figure
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
r
r
r
333).
24
23
22
Res.
Res.
Res.
8
7
6
rw
rw
rw
RM0453 Rev 5
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
RDR[8:0]
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
TDR[8:0]
rw
rw
rw
rw
RM0453
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
rw
rw
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