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M16C/64A Group
23.3.5
Special Mode 3 (IE Mode)
In this mode, 1 bit of IEBus is approximated by 1 byte of UART mode waveform.
Table 23.23 lists the Registers Used and Settings in IE Mode. Figure 23.34 shows the Bus Collision
Detect Function-Related Bits.
If the TXDi pin (i = 0 to 2, 5 to 7) output level and RXDi pin input level do not match, a UARTi bus
collision detect interrupt request is generated.
Use bits IFSR26 and IFSR27 in the IFSR2A register to enable the UART0/UART1 bus collision detect
function.
Table 23.23
Registers Used and Settings in IE Mode
Register
UiTB
(4)
UiRB
OER, FER, PER, SUM
UiBRG
UiMR
UiC0
UiC1
UjRRM
UiSMR
UiSMR2
UiSMR3
UiSMR4
U0RRM, U1RRM
UCON
CLKMD1, RCSP, 7
i = 0 to 2, 5 to 7; j = 2, 5 to 7
Notes:
1.
This table does not describe a procedure.
2.
Set bits 4 and 5 in registers U0C1 and U1C1 to 0. Bits U0IRS, U1IRS, U0RRM, and U1RRM are in the
UCON register.
3.
The TXD2 pin is N-channel open drain output. Nothing is assigned to the NCH bit in the U2C0 register. If
necessary, set it to 0.
Set the bits not listed above to 0 when writing to registers in IE mode
4.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Bits
0 to 8
Set transmission data.
0 to 8
Reception data can be read.
Error flag
0 to 7
Set bit rate.
SMD2 to SMD0
Set to 110b.
CKDIR
Select internal clock or external clock.
STPS
Set to 0.
PRY
Disabled because PRYE is 0
PRYE
Set to 0.
IOPOL
Select the TXD and RXD input/output polarity.
CLK1, CLK0
Select the count source for the UiBRG register.
CRS
Disabled because CRD is 1
TXEPT
Transmit register empty flag
CRD
Set to 1.
NCH
Select TXDi pin output format.
CKPOL
Set to 0.
UFORM
Set to 0.
TE
Set to 1 to enable transmission.
TI
Transmit buffer empty flag
RE
Set to 1 to enable reception.
RI
Reception complete flag
(2)
UjIRS
Select the source of UARTj transmit interrupt.
(2)
Set to 0.
, UiLCH, UiERE
0 to 3, 7
Set to 0.
ABSCS
Select the sampling timing to detect a bus collision.
ACSE
Set to 1 to use the auto clear function of the transmit enable bit.
SSS
Select the transmit start condition.
0 to 7
Set to 0.
0 to 7
Set to 0.
0 to 7
Set to 0.
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt.
Set to 0.
CLKMD0
Disabled because CLKMD1 is 0
Set to 0.
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
(1)
Function
(3)
.
Page 505 of 800
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