Oi Control Register (Sic) (I = 3, 4) - Renesas M16C/64A Series User Manual

M16C/64A Group
24.2.3 SI/Oi Control Register (SiC) (i = 3, 4)
SI/Oi Control Register (i = 3, 4)
b7 b6 b5 b4 b3 b2 b1
After setting the PRC2 bit in the PRCR register to 1 (write enabled), use the next instruction to write to
this register.
SMi1-SMi0 (Internal synchronous clock select bit) (b1-b0)
Select f1SIO or f2SIO by the PCLK1 bit in the PCLKR register.
Set the SiBRG register when changing bits SMi1 to SMi0.
SMi2 (SOUTi output disable bit) (b2)
When the SMi2 bit is set to 1 (SOUTi output disabled), the target pin becomes high-impedance
regardless of which function of the pin is being used.
SMi7 (SOUTi initial value set bit) (b7)
Set the SMi7 bit when the SMi3 bit is 0 (I/O port, serial interface disabled). The level selected by the
SMi7 bit is output from the SOUTi pin by setting the SMi3 bit to 1 and the SMi2 bit to 0 (SOUTi output).
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
b0
S3C
S4C
Bit symbol Bit Name
SMi0
Internal synchronous
clock select bit
SMi1
SMi2 SOUTi output disable bit
SMi3 SI/Oi port select bit
SMi4 CLK polarity select bit
SMi5 Bit order select bit
Synchronous clock
SMi6
select bit
SOUTi initial output set
SMi7
bit
24. Serial Interface SI/O3 and SI/O4
Address
0272h
0276h
Function
b1 b0
0 0 : f1SIO or f2SIO selected
0 1 : f8SIO selected
1 0 : f32SIO selected
1 1 : Do not set this value.
0 : SOUTi output enabled
1 : SOUTi output disabled (high-impedance)
0 : I/O port
serial interface disabled
1 : SOUTi output, CLKi function
serial interface enabled
0 : Transmit data is output at falling edge of
transmit/receive clock and receive data is
input at rising edge
1 : Transmit data is output at rising edge of
transmit/receive clock and receive data is
input at falling edge
0 : LSB first
1 : MSB first
0 : External clock
1 : Internal clock
Enabled when SMi6 is 0
0 : Low output
1 : High output
Reset Value
0100 0000b
0100 0000b
RW
RW
RW
RW
RW
RW
RW
RW
Page 522 of 800