Oi Bit Rate Register (Sibrg) (I = 3, 4); O3, 4 Control Register 2 (S34C2) - Renesas M16C/64A Series User Manual

M16C/64A Group
24.2.4 SI/Oi Bit Rate Register (SiBRG) (i = 3, 4)
SI/Oi Bit Rate Register (i = 3, 4)
b7
Use the MOV instruction to write to the SiBRG register.
Write to the SiBRG register after setting bits SMi1 to SMi0 in the SiC register, and while the serial
interface is neither transmitting nor receiving.
24.2.5 SI/O3, 4 Control Register 2 (S34C2)
SI/O3, 4 Control Register 2
b7 b6 b5 b4 b3 b2 b1
SM26 (SOUT3 output control bit) (b6)
SM27 (SOUT4 output control bit) (b7)
Bits SM26 and SM27 are enabled when the SMi6 bit in the SiC register is 1 (internal clock). Set the
SMi3 bit in the SiC register to 1 (serial interface enabled) after setting bits SM26 and SM27.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
b0
Symbol
S3BRG
S4BRG
SiBRG divides the count source by n + 1 where n = set
value
b0
Symbol
0
S34C2
Bit Symbol Bit Name
—
Reserved bit
(b0)
—
No register bit. If necessary, set to 0. Read as undefined value
(b1)
—
Reserved bit
(b2)
—
No register bits. If necessary, set to 0. Read as undefined value
(b5-b3)
SM26 SOUT3 output control bit
SM27 SOUT4 output control bit
Address
0273h
0277h
Function
Address
0278h
Set to 0
Set to 0
SOUT3 state after transmission
0 : High-impedance
1 : Last bit level retained
SOUT4 state after transmission
0 : High-impedance
1 : Last bit level retained
24. Serial Interface SI/O3 and SI/O4
Reset Value
Undefined
Undefined
Setting Range
00h to FFh
Reset Value
00XX X0X0b
Function
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RW
WO
RW
RW
—
RW
—
RW
RW