Renesas M16C/64A Series User Manual page 808

M16C/64A Group
32.14 Notes on Three-Phase Motor Control Timer Function
32.14.1 Timer A and Timer B
Refer to 17.5 "Notes on Timer A" and 18.5 "Notes on Timer B".
32.14.2 Influence of SD
When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:
P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W,
P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
32. Usage Notes
Page 775 of 800