Renesas M16C/64A Series User Manual page 85

M16C/64A Group
VCC1, VCC2
XIN
Microprocessor mode
BYTE = high
RESET
BCLK
Address
RD
WR
CS0
Microprocessor mode
BYTE = low
Address
RD
WR
CS0
Single-chip
mode
Address
Figure 6.3 Reset Sequence
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Must be equal to or
td(P-R)
1 × 20 cycles
more than
fOCO-S
tps + 8 × 60 cycles (max.)
fOCO-S
FFFFCh
FFFFDh
FFFFCh FFFFEh
Content of reset vector
FFFFCh
FFFFEh
6. Resets
Content of
FFFFEh
reset vector
Content of
reset vector
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