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M16C/64A Group
6.4.3
Power-On Reset Function
The power-on reset function can be used on the system in which VCC1 is Vdet0 or higher.
When the RESET pin is connected to VCC1 via a pull-up resistor, and the VCC1 voltage level rises
while the rise gradient is trth, the power-on reset function is enabled and the MCU resets the pins, CPU,
and SFRs. When the input voltage to the VCC1 pin reaches Vdet0 or above, the fOCO-S count starts.
When the fOCO-S count reaches 32, the internal reset signal becomes high and the MCU executes the
program at the address indicated by the reset vector. fOCO-S divided by 8 is automatically selected as
the CPU clock after reset.
The CWR bit in the RSTFR register becomes 0 (cold start) after power-on reset. Refer to 4. "Special
Function Registers (SFRs)" for the remaining SFR states after reset.
The internal RAM is not reset.
Use the voltage monitor 0 reset together with the power-on reset. Set the LVDAS bit in the OFS1
address to 0 (voltage monitor 0 reset enabled after hardware reset) and the VDSEL1 bit to 0 (Vdet0_2)
to use the power-on reset. In this case, the voltage monitor 0 reset is enabled (the VW0C0 bit and bit 6
in the VW0C register are 1 and the VC25 bit in the VCR2 register is 1). Do not set these bits to 0 by a
program.
Refer to 7. "Voltage Detector" for details of the voltage monitor 0 reset.
Figure 6.5 shows Power-On Reset Circuit and Operation Example. When a capacitor is connected to
the RESET pin, always keep voltage to the RESET pin in the range of VIH.
Internal reset signal
Figure 6.5
Power-On Reset Circuit and Operation Example
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
VCC1
4.7 kΩ
(reference)
RESET
V
det0
VCC1
V
por1
t
w(por)
(low active)
t
rth
1
× 32
fOCO-S
6. Resets
Page 54 of 800
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