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REVISION HISTORY
Rev.
Date
Page
2.00
Feb 07, 2011
76, 79
77, 80
Clock Generator
83
86
88
94
97
98
106
107
Power Control
110
111
113
114
115
118
120
120
121
121
122
123
123
124
125
125, 126 Figure 9.4 Setting and Canceling Slow Read Mode and Figure 9.5 Setting and Canceling Low
127
128
128
128
129
M16C/64A Group Hardware Manual
Table 7.7 Procedures for Setting Voltage Monitor 1 Interrupt/Reset Related Bits and
Table 7.8 Procedure for Setting Voltage Monitor 2 Interrupt/Reset Related Bits:
• Changed the sequence of the steps.
• Added note 3.
Figure 7.6 Voltage Monitor 1 Interrupt/Reset Operation Example and
Figure 7.8 Voltage Monitor 2 Interrupt/Reset Operation Example:
Changed note 1 from "VCC1 ≥ 2.7 V" to "recommended operation condition VCC1".
Figure 8.1 System Clock Generator:
• Changed the logic symbol connected to NMI and PM24.
• Changed a part of the main clock.
8.2.2 "System Clock Control Register 0 (CM0)":
Changed the second bullet of the CM06 bit explanation.
8.2.3 System Clock Control Register 1 (CM1): Changed the explanations for bits CM10 and CM15.
8.2.7 Processor Mode Register 2 (PM2): Added the last line in the PM21 bit explanation.
8.3.4 Sub Clock (fC): Integrated step (4) into step (3).
8.4.1 CPU Clock and BCLK: Changed the sixth line up from the bottom.
8.9.3 CPU Clock: Added the technical update number.
8.9.5 PLL Frequency Synthesizer: Added.
9.2.1 Flash Memory Control Register 0 (FMR0): Changed the FMR01 and FMSTP bit explanations.
9.2.2 Flash Memory Control Register 2 (FMR2): Changed the FMR23 bit explanation.
9.3.1.2 PLL Operating Mode: Deleted "high-speed mode".
9.3.1.6 Low Power Mode: Deleted the last 3 lines in the previous version.
Table 9.2 Clocks in Normal Operating Mode:
Deleted notes 2 to 6 in the previous version and newly added note 2.
Figure 9.2 Clock Divide Transition:
• Divided high-speed mode and medium-speed mode.
• Deleted "g" and "h" from 125 kHz on-chip oscillator mode.
9.3.3 Wait Mode: Changed the last 2 lines.
9.3.3.2 Entering Wait Mode: Added line 5 and below.
9.3.3.4 Exiting Wait Mode: Deleted the 2 paragraphs below the table.
Table 9.6 Resets and Interrupts to Exit Wait Mode and Conditions for Use:
• Changed the conditions for use in the Voltage monitor 1, Voltage monitor 2 row.
• Divided the Voltage monitor 1 reset, Voltage monitor 2 reset row from the Voltage monitor 0 reset
row and changed the conditions for use.
9.3.4.1 Entering Stop Mode: Added line 8 and below.
9.3.4.3 Exiting Stop Mode: Deleted the second paragraph in the previous version.
Table 9.8 Resets and Interrupts to Exit Stop Mode and Conditions for Use:
Changed the conditions for use in the Voltage monitor 0 reset row.
Figure 9.3 Stop and Restart of the Flash Memory:
• Changed the ranges of Stop Procedure and Restart Procedure.
• Deleted note 4.
9.4.2.1 Slow Read Mode: Added lines 3 and 4.
Current Consumption Read Mode: Deleted "Restore the CPU clock" from the canceling procedure.
9.5.2 A/D Converter: Deleted the explanation for when A/D conversion is performed.
9.6.1 CPU Clock: Added line 2.
9.6.2 Wait Mode:
• Added lines 4 and 5 to the first bullet.
• Deleted second bullet in the previous version and added the second to fifth bullets.
9.6.3 Stop Mode:
• Changed "until main clock oscillation is stabilized" in first bullet to "for 20 fOCO-S cycles or more".
• Added lines 6 and 7 to the third bullet.
• Deleted fourth bullet in the previous version and added fourth to eighth bullets.
9.6.4 Low Current Consumption Read Mode: Added the third bullet.
Description
Summary
C - 8
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