Peripheral Clock Select Register (Pclkr); Clock Prescaler Reset Flag (Cpsrf) - Renesas M16C/64A Series User Manual

M16C/64A Group
17.2.1

Peripheral Clock Select Register (PCLKR)

Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2 b1
0 0 0 0 0
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
17.2.2

Clock Prescaler Reset Flag (CPSRF)

Clock Prescaler Reset Flag
b7 b6 b5 b4 b3 b2 b1
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
b0
PCLKR
Bit Symbol Bit Name
Timers A and B clock select bit
(clock source for timers A and
PCLK0
B, the dead time timer, and
multi-master I
SI/O clock select bit
(clock source for UART0 to
PCLK1
UART2, UART5 to UART7,
SI/O3, and SI/O4)
—
Reserved bits
(b4-b2)
Clock output function
PCLK5 expansion bit
(enabled in single-chip mode)
—
Reserved bits
(b7-b6)
b0 Symbol
CPSRF
Bit Symbol Bit Name
—
No register bits. If necessary, set to 0. The read values are undefined.
(b6-b0)
CPSR Clock prescaler reset flag
Address
0012h
0: f2TIMAB/f2IIC
1: f1TIMAB/f1IIC
2
C-bus interface)
0: f2SIO
1: f1SIO
Set to 0
0: Selected by setting bits CM01 to CM00
in the CM0 register
1: Output f1
Set to 0
Address
0015h
Setting this bit to 1 initializes the prescaler
for the timekeeping clock.
(The read value is 0.)
Reset Value
0000 0011b
Function RW
RW
RW
RW
RW
RW
Reset Value
0XXX XXXXb
Function RW
RW
Page 256 of 800
17. Timer A
—