Renesas M16C/64A Series User Manual page 567

M16C/64A Group
I2C0 control register 1 (S3D0)
b7
SCL SDA
ICK1 ICK0 PEC PED
M M
SDAMM
(SDA)
b7
SSC
STSP
SIS SIP
SEL 4
I2C0 start/stop condition
control register (S2D0)
SCLMM
(SCL)
Figure 25.1 Multi-master I
Table 25.3 I/O Ports
Pin Name
SDAMM
SCLMM
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
b0
WIT SIM
I2C0 status register 1 (S11)
b7
AAS AAS AAS
2 1 0
SCL/SDA
Interrupt
interrupt
generator
request
Data
Noise filter
controller
b0
AL
SSC SSC SSC SSC
circuit
3 2 1 0
BB
circuit
b7
Clock
Noise ACK ACK
controller FAST
CLK BIT MODE
filter
I2C0 clock control
register (S20)
2
I C-bus system clock
2
C-bus Interface Block Diagram
I/O
I/O
I/O pin for SDA (N-channel open drain output)
I/O I/O pin for SCL (N-channel open drain output)
I2C0 address register 2 (S0D2)
b7 b0
SAD SAD SAD SAD SAD SAD SAD
6 5 4 3 2 1 0
I2C0 address register 1 (S0D1)
b7
SAD SAD SAD SAD SAD SAD
6 5 4 3 2
I2C0 address register 0 (S0D0)
b0 b7
SAD SAD SAD
6 5
SA Address comparator
D6
b7 b0
I2C0 data shift register (S00)
I2C0 control
register 2 (S4D0)
SCPI MSL TOS
ICK4 ICK3 ICK2 TOF TOE
N AD EL
Timeout
detector
b0
CCR CCR CCR CCR CCR
4 3 2 1 0
Clock divider
(fVIIC)
fIIC
System clock selector
Function
25. Multi-master I
b0
SAD
1 0
b0
SAD SAD SAD SAD
4 3 2 1 0
Interrupt
generator
I2C0 status
register 0 (S10)
b7
AL AAS
MST TRX BB PIN
b7
TISS IHR ALS ES0 BC2 BC1 BC0
I2C0 control register 0
(S1D0)
Bit counter
PCLKR register
PCLK0 = 1
f1IIC
f2IIC
PCLK0 = 0
2
C-bus Interface
2
I C-bus
interface
interrupt
request
b0
ADR
LRB
0
b0
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