Renesas M16C/64A Series User Manual page 347

M16C/64A Group
Timer Mode
Timer Bi Mode Register (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1
0 0 0
TCK1 and TCK0 (Count source select bit) (b7-b6)
These bits are enabled when the TCS3 or TCS7 bit in registers TBCS0 to TBCS3 is set to 0 (bits TCK0
to TCK1 enabled).
Select f1TIMAB or f2TIMAB by the PCLK0 bit in the PCLKR register.
Count operations
0000h
TBiS bit in the
TABSR register or
TBSR register
IR bit
in the TBiIC register
i = 0 to 5
The above assumes the following:
•
The value in the TBi register (n) = 0004h
Figure 18.4 Operation Example in Timer Mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
b0
TB0MR to TB2MR
0
TB3MR to TB5MR
Bit Symbol Bit Name
TMOD0
Operation mode select bit
TMOD1
MR0
Set to 0 in timer mode.
MR1
—
No register bit. If necessary, set to 0. The read value is undefined.
(b4)
Write 0 in timer mode.
MR3
The read value is undefined in timer mode.
TCK0
Count source select bit
TCK1
Count start
n
Address
033Bh to 033Dh
031Bh to 031Dh
b1 b0
0 0 : Timer mode
b7 b6
0 0 : f1TIMAB or f2TIMAB
0 1 : f8TIMAB
1 0 : f32TIMAB
1 1 : fC32
Underflow
n+1
and reload
Set to 0 by accepting an interrupt request, or by a program.
Reset Value
00XX 0000b
00XX 0000b
Function
Count stop
by TBiS bit
Page 314 of 800
18. Timer B
RW
RW
RW
RW
RW
—
RO
RW
RW