Cpu Clock - Renesas M16C/64A Series User Manual

M16C/64A Group
Table 9.2 Clocks in Normal Operating Mode
Mode
High-speed mode
Medium-speed mode
PLL operating mode
125 kHz on-chip oscillator
mode
125 kHz on-chip oscillator
low power mode
Low-speed mode
Low power mode
CM11 : Bit in the CM1 register
CM21 : Bit in the CM2 register
Notes:
1. Select by setting the CM06 bit in the CM0 register and bits CM17 to CM16 in the CM1 register.
2. The peripheral clock is enabled when each clock is supplied. Refer to 8. "Clock Generator" for the
clock supply method.
Table 9.3 Clock-Related Bit Setting and Modes
Mode
High-speed mode,
medium-speed mode
PLL operating mode
125 kHz on-chip oscillator mode
125 kHz on-chip oscillator low
power mode
Low-speed mode
Low power mode
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012

CPU Clock

Main clock
(1)
divided by 1
Main clock divided by 1
Main clock
(1)
divided by n
PLL clock
PLL clock divided by 1
(1)
divided by n
fOCO-S
fOCO-S divided by 1
(1)
divided by n
fOCO-S
fOCO-S divided by 1
(1)
divided by n
A ny of the following:
Main clock divided by 1
(when the CM21 is 0 and the CM11 is 0)
fC PLL clock divided by 1
(when the CM21 is 0 and the CM11 is 1)
fOCO-S divided by 1
(when the CM21 is 1)
fOCO-S divided by 1
fC
(when the CM21 is 1)
CM2 Register
CM21
0
0
1
1
−
−
Peripheral Clocks
f1
CM1 Register
CM14 CM11 CM07
−
0 0
−
1 0
0 0 0
0 0 0
−
0 1
−
0 1
9. Power Control
(2)
fC, fC32 fOCO-S
Enabled Enabled
Enabled Enabled
Enabled Enabled
Enabled Enabled
Enabled Enabled
CM0 Register
CM05 CM04
−
0
−
0
−
0
−
1
0 1
1 1
−
: 0 or 1
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