Uarti Special Mode Register 4 (Uismr4) (I = 0 To 2, 5 To 7) - Renesas M16C/64A Series User Manual

M16C/64A Group
23.2.9

UARTi Special Mode Register 4 (UiSMR4) (i = 0 to 2, 5 to 7)

UARTi Special Mode Register 4 (i = 0 to 2, 5 to 7)
b7 b6 b5 b4 b3 b2 b1
STAREQ (Start condition generate bit) (b0)
The STAREQ bit becomes 0 when a start condition is generated.
This bit is used in master mode of I
2
register to 1 (I C mode). Do not set this bit to 1 when the IICM bit is 0.
RSTAREQ (Restart condition generate bit) (b1)
The RSTAREQ bit becomes 0 when a restart condition is generated.
This bit is used in master mode of I
2
register to 1 (I C mode). Do not set this bit to 1 when the IICM bit is 0.
STPREQ (Stop condition generate bit) (b2)
The STPREQ bit becomes 0 when a stop condition is generated.
This bit is used in master mode of I
2
register to 1 (I C mode). Do not set this bit to 1 when the IICM bit is 0.
STSPSEL (SCL, SDA output select bit) (b3)
This bit is used in master mode of I
2
register to 1 (I C mode). Do not set this bit to 1 when the IICM bit is 0.
Set the STSPSEL bit to 1 (select start condition/stop condition generate circuit) after setting the
STARREQ, RSTAREQ, or STPREQ bit to 1 (start).
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
b0
U0SMR4, U1SMR4, U2SMR4
U5SMR4, U6SMR4, U7SMR4
Bit Symbol Bit Name
STAREQ Start condition generate bit
Restart condition generate
RSTAREQ
bit
STPREQ Stop condition generate bit
STSPSEL SCL, SDA output select bit
ACKD ACK data bit
ACKC ACK data output enable bit
SCLHI SCL output stop bit
SWC9 SCL wait auto insert bit 3
2
C mode. To set this bit to 1, preset the IICM bit in the UiSMR
2
C mode. To set this bit to 1, preset the IICM bit in the UiSMR
2
C mode. To set this bit to 1, preset the IICM bit in the UiSMR
2
C mode. To set this bit to 1, preset the IICM bit in the UiSMR
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Address
0244h, 0254h, 0264h
0284h, 0294h, 02A4h
Function
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Select serial I/O circuit
1 : Select start condition/stop condition
generate circuit
0 : ACK
1 : NACK
0 : Serial data output
1 : ACK data output
If stop condition is detected,
0 : Do not stop SCLi output
1 : Stop SCLi output
0 : No wait-state/wait-state cleared
1 : Hold the SCLi pin low after the ninth bit
of the SCLi is received
Reset Value
00h
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
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