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M16C/64A Group
7.4.3.2
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset
Table 7.7 lists Procedures for Setting Voltage Monitor 1 Interrupt/Reset Related Bits.
Table 7.7
Procedures for Setting Voltage Monitor 1 Interrupt/Reset Related Bits
Step
Voltage monitor 1
interrupt
1
Set the VW12E bit in the VWCE register to 1 (voltage monitors 1 and 2 enabled).
2
Set bits VD1LS3 to VD1LS0 in the VD1LS register to select Vdet1.
3
Set the VC26 bit in the VCR2 register to 1 (voltage detector 1 enabled).
4
Wait for td(E-A).
Use bits VW1F1 and VW1F0 in the VW1C
5
register to select the digital filter sampling
clock.
Set the VW1C1 bit in the VW1C register to 0
(2)
6
(digital filter enabled).
Set the VW1C6 bit in
the VW1C register to 0
(2)
7
(voltage monitor 1
interrupt).
8
Set the VW1C2 bit in the VW1C register to 0 (Vdet1 passage not detected).
Set the CM14 bit in the CM1 register to 0 (125
9
kHz on-chip oscillator on)
10
Wait for digital filter sampling clock x 3 cycles. - (no wait time)
11
Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled).
Notes:
1.
Set the VW1C7 bit to 1 (when VCC1 reaches Vdet1 or below) for the voltage monitor 1 reset.
2.
When the VW1C0 bit is 0, steps 5, 6, and 7 can be executed simultaneously (with one instruction).
3.
If above setting is performed while voltage monitor 1 interrupt/reset is disabled (VW1C0 bit in the
VW1C register is 0, VC26 bit in the VCR2 register is 0) and VCC1 < Vdet1 (or VCC1 > Vdet1) is
detected before enabling voltage monitor 1 interrupt/reset (step 11), an interrupt does not occur.
When VCC1 < Vdet1 (or VCC1 > Vdet1) is detected while executing steps 9 to 11, the VW1C2 bit
becomes 1.
When using this result detected between steps 9 and 11, read the VW1C2 bit after step 11. If the
bit is 1, execute the process to be performed after detecting the VCC1 < Vdet1 (or VCC1 > Vdet1).
When ignoring the result detected between steps 9 and 11, set the VW1C2 bit to 0 after step 11.
When using voltage monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1
bit in the VW1C register to 1 (digital filter disabled).
When voltage monitor 1 reset is generated, the LVD1R bit in the RSTFR register becomes 1 (voltage
monitor 1 reset detected). Refer to 6.4.5 "Voltage Monitor 1 Reset" for status after reset.
Figure 7.6 shows Voltage Monitor 1 Interrupt/Reset Operation Example.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
When Using the Digital Filter
Voltage monitor 1
Set the VW1C6 bit in
the VW1C register to 1
(voltage monitor 1
reset).
When Not Using the Digital Filter
Voltage monitor 1
reset
interrupt
Use the VW1C7 bit in the VW1C register to
select the timing of the interrupt and reset
request.
Set the VW1C1 bit in the VW1C register to 1
(digital filter disabled).
Set the VW1C6 bit in
the VW1C register to 0
(voltage monitor 1
interrupt).
-
7. Voltage Detector
Voltage monitor 1
(1)
Set the VW1C6 bit in
the VW1C register to 1
(voltage monitor 1
reset).
reset
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