Renesas M16C/64A Series User Manual page 621

M16C/64A Group
26.2.3 CEC Function Control Register 3 (CECC3)
CEC Function Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
CTXDEN (Transmit enable bit) (b0)
CRXDEN (Receive enable bit) (b1)
When changing the values of these bits, transmission/reception is enabled or disabled after one or
more cycles of the clock source elapses.
When setting the CTXDEN bit to 0 while transmitting/receiving, transmitting is disabled after ACK
completion. In the same way, when setting the CRXDEN bit to 0 while transmitting/receiving, reception
is disabled after ACK completion.
CREGCLR (Receive edge detect flag clear bit) (b2)
The CREGFLG bit in the CECC4 register becomes 0 by setting the CREGCLR bit to 1 when CEC input
is Hi-Z.
The CREGCLR bit retains the value written to it. In order set the CREGFLG bit to 0 again by setting the
CREGCLR bit to 1, first set the CREGCLR bit to 0, then set it to 1.
When setting the CREGCLR bit to 1 while CEC input is low, the CREGFLG bit becomes 0. If the
CREGCLR bit is set to 0 after that, the CREGFLG bit becomes 1.
Figure 26.2 shows the Operation of Bits CREGFLG and CREGCLR.
CEC
Becomes 1 when CEC
is low.
CREGFLG bit
CREGCLR bit
CREGCLR: Bit in the CECC3 register
CREGFLG: Bit in the CECC4 register
Figure 26.2 Operation of Bits CREGFLG and CREGCLR
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Symbol
CECC3
Bit Symbol
Bit Name
CTXDEN Transmit enable bit
CRXDEN Receive enable bit
Receive edge detect flag
CREGCLR
clear bit
CEOMI EOM disable bit
—
No register bits. If necessary, set to 0. Read as undefined value
(b7-b4)
The CREGFLG bit
becomes 0 by setting
the CREGCLR bit to 0
when CEC is high.
26. Consumer Electronics Control (CEC) Function
Address
0352h
Function
0: Disabled
1: Enabled
0: Disabled
1: Enabled
The CREGFLG bit in the CECC4
register becomes 0 by setting 1 to
this bit
0: EOM enabled
1: EOM disabled (EOM ignored)
When CEC is low, the
CREGFLG bit is 0
while the CREGCLR
bit is 1.
Reset Value
XXXX 0000b
RW
RW
RW
RW
RW
—
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