Reception Interrupt - Renesas M16C/64A Series User Manual

M16C/64A Group
Some interrupts of UART0 to UART2 and UART5 to UART7 share interrupt vectors and interrupt
control registers with other peripheral functions. When using these interrupts, select them by interrupt
source select registers. Table 23.27 lists Interrupt Selection in UART0 to UART2 and UART5 to UART7.
Table 23.27 Interrupt Selection in UART0 to UART2 and UART5 to UART7
UART0 start/stop condition detection, bus collision detection
UART1 start/stop condition detection, bus collision detection
UART5 start/stop condition detection, bus collision detection
UART5 transmission, NACK
UART6 start/stop condition detection, bus collision detection
UART6 transmission, NACK
UART7 start/stop condition detection, bus collision detection
UART7 transmission, NACK
In the following modes, an interrupt request can be generated by rewriting bit values.
•
Special mode 1 (I
Set the IR bit in the interrupt control register of UARTi to 0 (interrupt not requested), when the
following bits are changed:
Bits SMD2 to SMD0 in the UiMR register, the IICM bit in the UiSMR register, the IICM2 bit in the
UiSMR2 register, the CKPH bit in the UiSMR3 register
•
Special mode 4 (SIM mode)
After reset, a transmit interrupt request is generated by setting bits U2IRS and U2ERE in the U2C1
register to 1 (transmission completed, error signal output), then setting the TE bit to 1 (transmission
enabled) and the transmission data to the U2TB register. Therefore, when using SIM mode, make
sure to set the IR bit to 0 (interrupt not requested) after setting these bits.
23.4.2

Reception Interrupt

•
The case that bits SMD2 to SMD0 in the UiMR register are not set to 010b (I
When the RI bit in the UiC1 register is changed from 0 (no data in the UiRB register) to 1 (data
present in the UiRB register), the IR bit in the SiRIC register is automatically set to 1 (interrupt
requested).
If an overrun error occurs (when the RI bit is 1, the next data is received), the RI bit remains 1,
and therefore, the IR bit in the SiRIC register remains unchanged.
•
The case that bits SMD2 to SMD0 in the UiMR register are set to 010b (I
When the RI bit in the UiC1 register is changed from 0 (no data in the UiRB register) to 1 (data
present in the UiRB register), the IR bit in the SiRIC register is automatically set to 1 (interrupt
requested).
When an overrun error occurs, the IR bit in the SiRIC register also becomes 1.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Interrupt Source
2
C mode)
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Interrupt Source Select Register Settings
Register Bit
IFSR2A IFSR26
IFSR2A IFSR27
IFSR3A IFSR33
IFSR3A IFSR34
IFSR3A IFSR35
IFSR3A IFSR36
IFSR2A IFSR24
IFSR2A IFSR25
2
C mode)
2
C mode)
Setting Value
1
1
0
0
0
0
0
0
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