Renesas M16C/64A Series User Manual page 844

REVISION HISTORY
Rev. Date
Page
2.00 Feb 07, 2011 429
430
433, 441 22.3.3.1 Setting Procedure, 22.3.5.1 Setting Procedure: Changed the procedure.
433
437, 441 Table 22.17 and Table 22.20 Registers and Setting Values in Input Capture Mode:
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442
442
443
445
445
445
Serial Interface UARTi
Chap. 23. Changed the sequence of the register diagrams.
Chap. 23. 23.3.1.1 and 23.3.2.2 Transmit/Receive Circuit Initialization: Deleted.
Chap. 23. 23.3.3.4 Transmit/Receive Clock: Deleted.
Chap. 23. Figure 23.24 and Figure 23.25 Transmission and Reception Timing: Deleted.
Chap. 23. 23.5.3 UART (Clock Asynchronous Serial I/O) Mode: Deleted.
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M16C/64A Group Hardware Manual
Figure 22.8 Receive Buffer and Compare Function: Deleted the arrows from the PMC0RBIT register.
22.3.3 Pattern Match Mode (Combined Operation of PMC0 and PMC1):
Changed "detected in PM1" in line 2 to "detected in PM0".
22.3.3.2 Header and Special Data Detection: Changed lines 1 to 2 below Table 22.14.
Deleted the PMCiBC row.
Figure 22.9 Operations in Input Capture Mode: Changed the timing when the IR bit becomes 1.
Table 22.21 Interrupt Source of Remote Control Signal Receiver i Interrupt (i = 0, 1):
Added the Interrupt Request Bit column.
22.4 Interrupts: Deleted the last paragraph.
Figure 22.10 Remote Control Signal Receiver Interrupts:
Changed the interrupt request names to symbols.
22.5.1 Starting/Stopping PMCi: Changed the last 3 lines from lines 5 to 6 in the previous version.
22.5.2 Reading the Register: Added the last 2 lines.
22.5.3 Rewriting the Register: Added.
23.2.2 UARTi Transmit/Receive Mode Register (UiMR) (i = 0 to 2, 5 to 7):
Added the explanation of bits SMD2 to SMD0.
23.2.3 UARTi Bit Rate Register (UiBRG) (i = 0 to 2, 5 to 7): Added the setting range in I
23.2.4 UARTi Transmit Buffer Register (UiTB) (i = 0 to 2, 5 to 7):
2
Added "or I C mode" after "When character length is 9 bits long,".
23.2.9 UARTi Special Mode Register 4 (UiSMR4) (i = 0 to 2, 5 to 7):
• Changed the bit names of bits SCLHI and SWC9.
• Changed the functions of bits STSPSEL, SCLHI, and SWC9.
• Changed and added all the bit explanations.
23.2.11 UARTi Special Mode Register 2 (UiSMR2) (i = 0 to 2, 5 to 7):
• Changed the bit names of bits SWC, ALS, and STAC.
• Changed the functions of bits other than b7.
Table 23.5 Clock Synchronous Serial I/O Mode Specifications: Changed note 1.
23.3.1.8 and 23.3.2.7 Processing When Terminating Communication or When an Error Occurs: Added.
Figure 23.13 Receive Timing in UART Mode:
Changed "UiBRG countsource" to "Clock divided by UiBRG".
2
Table 23.14 I C Mode Specifications:
• Changed "00h to FFh" to "03h to FFh" in the Transmit/receive clock row.
• Changed the Interrupt request generation timing row.
• Changed note 1.
2
Figure 23.18 I C Mode Block Diagram:
Changed "9th bit falling edge" to "8th bit falling edge" below the CLK control.
Figure 23.19 Internal Clock Configuration: Added.
Table 23.16 Registers Used and Settings in I
Table 23.17 Registers Used and Settings in I
Changed the function of the SWC bit and CKPH bit.
C - 11
Description
Summary
2
C Mode (1/2): Changed the function of the UiTB register.
2
C Mode (2/2):
2
C mode.