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M16C/64A Group
32.12 Notes on Timer A
32.12.1 Common Notes on Multiple Modes
32.12.1.1 Register Setting
The timer stops after reset. Set the mode, count source, counter value, etc., using registers TAiMR,
TAi, TAi1, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS, PCLKR, and bits TAZIE, TA0TGL,
and TA0TGH in the ONSF register before setting the TAiS bit in the TABSR register to 1 (count
started) (i = 0 to 4).
Always make sure registers TAiMR, UDF, TRGSR, PWMFS, TACS0 to TACS2, TAPOFS, PCLKR,
and bits TAZIE, TA0TGL, TA0TGH in the ONSF register are modified while the TAiS bit is 0 (count
stopped), regardless of whether after reset or not.
32.12.1.2 Event or Trigger
When bits TAiTGH to TAiTGL in the registers ONSF or TRGSR are 01b, 10b, or 11b, an event or a
trigger occurs when an interrupt request of the selected timer is generated. An event or trigger occurs
while an interrupt is disabled because an interrupt request signal is generated regardless of the I flag,
IPL, or interrupt control registers.
For some modes of the timers selected using bits TAiTGH to TAiTGL, an interrupt request is gener-
ated by a source other than overflow or underflow.
For example, when using pulse-period measurement mode or pulse-width measurement mode in
timer B2, an interrupt request is generated at an active edge of the measurement pulse. For details,
refer to the "Interrupt request generation timing" in each mode's specification table.
32.12.1.3 Influence of SD
When a low-level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 (three-
phase output forcible cutoff by input on SD pin enabled), the following pins become high-impedance:
P7_2/CLK2/TA1OUT/V, P7_3/ CTS2 / RTS2 /TA1IN/ V , P7_4/TA2OUT/W,
P7_5/TA2IN/ W , P8_0/TA4OUT/RXD5/SCL5/U, P8_1/TA4IN/ CTS5 / RTS5 / U
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
32. Usage Notes
Page 769 of 800
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