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M16C/64A Group
32.17.3.5 Restrictions on the Bit Rate When Using the UiBRG Count Source
2
In I
C mode, set the UiBRG register to a value of 03h or greater.
A maximum of three UiBRG count source cycles are necessary until the internal circuit
acknowledges the SCL clock level. The connectable I
UiBRG count source speed. If a value between 00h to 02h is set to the UiBRG register, bit slippage
may occur.
32.17.3.6 Restart Condition in Slave Mode
When a restart condition is detected in slave mode, the successive processes may not be executed
correctly. In slave mode, do not use a restart condition.
32.17.3.7 Requirements to Start Transmission/Reception in Slave Mode
When transmission/reception is started in slave mode and the TXEPT bit in the UiC0 register is 1 (no
data present in transmit register), meet the last requirement when the external clock is high.
Requirements to start transmission (in no particular order):
•
The TE bit in the UiC1 register is 1 (transmission enabled).
•
The TI bit in the UiC1 register is 0 (data present in the UiTB register).
Requirements to start reception (in no particular order):
•
The RE bit in the UiC1 register is 1 (reception enabled).
•
The TE bit in the UiC1 register is 1 (transmission enabled).
•
The TI bit in the UiC1 register is 0 (data present in the UiTB register).
32.17.4 Special Mode 4 (SIM Mode)
(Technical update number: TN-M16C-101-0309)
After reset, a transmit interrupt request is generated by setting bits U2IRS and U2ERE in the U2C1
register to 1 (transmission completed, error signal output), then setting the TE bit to 1 (transmission
enabled) and the transmission data to the U2TB register. Therefore, when using SIM mode, make sure
to set the IR bit to 0 (interrupt not requested) after setting these bits.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
2
C-bus bit rate is one-third or less than the
32. Usage Notes
Page 783 of 800
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