Clock Mode Transition Procedure - Renesas M16C/64A Series User Manual

M16C/64A Group
9.3.2

Clock Mode Transition Procedure

Figure 9.1 shows Clock Mode Transition. Arrows indicate possible mode transitions.
Normal
Operating Mode
PLL operating mode
Figure 9.1 Clock Mode Transition
To start or stop clock oscillations, or to change modes in normal operating mode, follow the instructions
below.
•
Enter a different mode after the clock for that mode stabilizes completely.
•
When stopping a clock, do it after mode transition is completed. Do not stop the clock at the same
time as mode transition.
•
When entering a new mode from PLL operating mode, high-speed or medium-speed mode, or 125
kHz on-chip oscillator mode, or entering one of these modes from another mode, select divide by 8
or divide by 16.
•
When the clock division ratio is switched in PLL operating mode or high-speed or medium-speed
mode, the ratio changes in the order shown in Figure 9.2.
•
To change the mode, follow procedures a to c, and e to h listed below. For details on register and
bit access, refer to 9.2 "Registers". Letters a to c, and e to h correspond to those in Figure 9.1
"Clock Mode Transition" and Figure 9.2 "Clock Divide Transition".
•
For details on oscillator start and stop, refer to 8.3.1 "Main Clock" to 8.3.4 "Sub Clock (fC)".
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
a
High-speed or
c
medium-speed
b
mode
Interrupt
or
reset
Wait mode
CPU operation stop
Reset
wait mode and stop mode enabled
125 kHz on-chip
oscillator mode
e
e
f
f
Low-speed mode
a
Interrupt
or
WAIT
reset
instruction
All oscillations stop
9. Power Control
Transitions to
g 125 kHz on-chip
oscillator low power
h
mode
g
Low power mode
h
CM10 = 1
Stop mode
CM10 : Bit in the CM1 register
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