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M16C/64A Group
Switching Characteristics
(V
= V
= 3 V, V
CC1
CC2
SS
31.3.4.3
In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Table 31.57
Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus)
Symbol
t
Address output delay time
d(BCLK-AD)
t
Address output hold time (in relation to BCLK)
h(BCLK-AD)
t
Address output hold time (in relation to RD)
h(RD-AD)
t
Address output hold time (in relation to WR)
h(WR-AD)
t
Chip select output delay time
d(BCLK-CS)
t
Chip select output hold time (in relation to BCLK)
h(BCLK-CS)
t
Chip select output hold time (in relation to RD)
h(RD-CS)
t
Chip select output hold time (in relation to WR)
h(WR-CS)
t
RD signal output delay time
d(BCLK-RD)
t
RD signal output hold time
h(BCLK-RD)
t
WR signal output delay time
d(BCLK-WR)
t
WR signal output hold time
h(BCLK-WR)
t
Data output delay time (in relation to BCLK)
d(BCLK-DB)
t
Data output hold time (in relation to BCLK)
h(BCLK-DB)
t
Data output delay time (in relation to WR)
d(DB-WR)
t
Data output hold time (in relation to WR)
h(WR-DB)
t
ALE signal output delay time (in relation to BCLK)
d(BCLK-ALE)
t
ALE signal output hold time (in relation to BCLK)
h(BCLK-ALE)
t
ALE signal output delay time (in relation to Address)
d(AD-ALE)
t
ALE signal output hold time (in relation to Address)
h(AD-ALE)
t
RD signal output delay from the end of address
d(AD-RD)
t
WR signal output delay from the end of address
d(AD-WR)
t
Address output floating start time
dz(RD-AD)
Notes:
1.
Calculated according to the BCLK frequency as follows:
2.
Calculated according to the BCLK frequency as follows:
9
(
) 10
×
n 0.5
–
----------------------------------- - 50 ns
–
f
(
)
BCLK
3.
Calculated according to the BCLK frequency as follows:
4.
Calculated according to the BCLK frequency as follows:
5.
When using multiplexed bus, set f
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
= -20 ° C to 85 ° C/-40 ° C to 85 ° C unless otherwise specified)
= 0 V, at T
opr
Parameter
[
]
n is 2 for 2 waits setting, 3 for 3 waits setting.
12.5 MHz or less.
(BCLK)
(5)
Measuring
Condition
See
Figure 31.27
9
×
0.5 10
[
]
--------------------- - 10 ns
–
f
(
)
BCLK
9
×
0.5 10
[
]
--------------------- - 40 ns
–
f
(
)
BCLK
9
×
0.5 10
[
]
--------------------- - 15 ns
–
f
(
)
BCLK
31. Electrical Characteristics
V
= V
= 3 V
CC1
CC2
Standard
Unit
Min.
Max.
50
ns
0
ns
(Note 1)
ns
(Note 1)
ns
50
ns
0
ns
(Note 1)
ns
(Note 1)
ns
40
ns
0
ns
40
ns
0
ns
50
ns
0
ns
(Note 2)
ns
(Note 1)
ns
25
ns
− 4
ns
(Note 3)
ns
(Note 4)
ns
0
ns
0
ns
8
ns
Page 746 of 800
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