Renesas M16C/64A Series User Manual page 849

REVISION HISTORY
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2.00 Feb 07, 2011 729
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Usage Notes
Chap. 32. 32.1 OFS1 Address and ID Code Storage: Deleted.
Chap. 32. 32.24.1 Functions to Prevent Flash Memory from Being Rewritten: Deleted.
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780 to 781 32.17.3.3 Low/High-level Input Voltage and Low-level Output Voltage to 32.17.3.7 Requirements to
M16C/64A Group Hardware Manual
Table 31.38 Electrical Characteristics (1):
• Added rows for the CEC value to Leakage current in powered-off state, V
• Added "ZP, IDU, IDV, IDW" to the V
Table 31.39 Electrical Characteristics (2): Changed "VCC1 = 5.0 V" to "VCC1 = 3.0 V" in the During
flash memory program and During flash memory erase rows.
Table 31.40 "Electrical Characteristics (3)":
• Added new part numbers above the table.
• Changed "VCC1 = 5.0 V" to "VCC1 = 3.0 V" in the During flash memory program and During
flash memory erase rows.
Table 31.54 Memory Expansion Mode and Microprocessor Mode:
Changed RDY input setup time from 40.
32.2.1 Register Settings: Added the description for read-modify-write instructions.
Table 32.2 Read-Modify-Write Instructions: Added.
32.4.1 Power Supply Rising Gradient: Deleted "VCC1 ≤ 3.6 V" from the table.
Figure 32.2 SVCC Timing (3.6 V < VCC1), Figure 32.3 SVCC Timing (VCC1 ≤ 3.6 V):
Revised from Figure 32.2 SVCC Timing.
32.4.2 Power-On Reset:
Added the "the VDSEL1 bit to 0 (Vdet0_2)" to the setting for power-on reset.
32.5.3 CPU Clock: Added the technical update number.
32.5.5 PLL Frequency Synthesizer: Added.
32.6.1 CPU Clock: Added line 3.
32.6.2 Wait Mode:
• Added lines 4 and 5 to the first bullet.
• Deleted second bullet in the previous version and added the second to fifth bullets.
32.6.3 Stop Mode:
• Changed "until main clock oscillation is stabilized" in first bullet to "for 20 fOCO-S cycles or
more".
• Added lines 6 and 7 to the third bullet.
• Deleted fourth bullet in the previous version and added fourth to eighth bullets.
32.6.4 Low Current Consumption Read Mode: Added the third bullet.
32.6.5 Slow Read Mode: Added.
32.7.4 HOLD: Added.
32.9.2 SP Setting: Deleted the descriptions regarding the NMI interrupt.
32.9.3 NMI Interrupt: Added the second bullet.
32.9.5 Rewriting the Interrupt Control Register and 32.9.6 Instruction to Rewrite the Interrupt
Control Register:
Rewritten from 32.10.5 Rewriting the Interrupt Control Register in the previous version.
32.11.1 Write to the DMAE Bit in the DMiCON Register (i = 0 to 3):
Added the technical update number.
32.12.1.2 Event or Trigger: Added.
32.12.1.3 Influence of SD: Added.
32.13.3.2 Event: Added.
32.13.4.3 Event or Trigger: Added.
32.14.2 Influence of SD: Changed the section title and description.
32.16.1 Starting/Stopping PMCi: Changed the last 3 lines from lines 5 to 6 in the previous version.
32.16.2 Reading the Register: Added the last 2 lines.
32.16.3 Rewriting the Register: Added.
32.17.2.2 Transmission and 32.17.2.3 Reception:
Changed the explanations about the external clock level into bullet lists.
32.17.3.1 Generating Start and Stop Conditions: Added the technical update number.
Start Transmission/Reception in Slave Mode: Added.
C - 16
Description
Summary
-V row.
T+ T-
-V , and V .
T+ T- OL