Renesas R-IN32M3 Series User Manual
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Renesas R-IN32M3 Series User Manual

Renesas R-IN32M3 Series User Manual

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R-IN32M3 Series
User's Manual
・R-IN32M3-EC
MC-10287BF1-HN4-A
MC-10287BF1-HN4-M1-A
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com)
Document number: R18UZ0003EJ0501
Issue date: Jan. 12, 2021
Renesas Electronics
www.renesas.com

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Summary of Contents for Renesas R-IN32M3 Series

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
  • Page 3 Instructions for the use of product In this section, the precautions are described for over whole of CMOS device. Please refer to this manual about individual precaution. When there is a mention unlike the text of this manual, a mention of the text takes first priority 1.Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
  • Page 4 R-IN32M3 Series Datasheet R18DS0008EJ**** R-IN32M3-CL User’s Manual R18UZ0005EJ**** R-IN32M3 Series User’s Manual (Peripheral Modules) R18UZ0007EJ**** R-IN32M3 Series Programming Manual (Driver edition) R18UZ0009EJ**** R-IN32M3 Series Programming Manual (OS edition) R18UZ0011EJ**** R-IN32M3 Series User’s Manual (Board design edition) R18UZ0021EJ**** R-IN32M3-EC User’s Manual This manual...
  • Page 5 2. Notation of Numbers and Symbols Weight in data notation: Left is high-order column, right is low-order column Active low notation: xxxZ (capital letter Z after pin name or signal name) or xxx_N (capital letter _N after pin name or signal name) or xxnx (pin name or signal name contains small letter n) Note: Explanation of (Note) in the text...
  • Page 6 Contents Overview ................................ 1 Introduction................................. 1 Overview ................................2 Internal Block Diagram ............................4 Pin Assignments (Top View) ..........................5 Base Addresses of the System Registers Area ....................6 Pin Functions ..............................7 List of Pins ................................8 2.1.1 Ethernet Pins .............................. 8 2.1.2 EtherCAT Slave Controller Pins ......................
  • Page 7 2.3.4 System Pins .............................. 38 2.3.5 Test Pins ..............................38 2.3.6 Port Pins ..............................39 2.3.7 Operation Mode Setting Pins ........................40 2.3.8 CC-Link Pin (Intelligent Device Station, Remote Device Station) ............40 2.3.9 Trace Pins ..............................40 Memory Maps .............................. 41 Exception Handling ............................
  • Page 8 6.9.2 Write Register Protection Register (WR_REG_PROTECT) ..............72 6.9.3 ESC Write Enable Register (ESC_WR_ENABLE) ................. 73 6.9.4 ESC Write Protection Register (ESC_WR_PROTECT) ................. 73 6.10 Data Link Layer Registers ..........................74 6.10.1 ESC Reset ECAT Register (ESC_RESET_ECAT) ................. 74 6.10.2 ESC Reset PDI Register (ESC_RESET_PDI) ..................
  • Page 9 6.16 SII EEPROM Interface Registers ........................100 6.16.1 EEPROM Configuration Register (EEP_CONF) .................. 100 6.16.2 EEPROM PDI Access State Register (EEP_STATE) ................101 6.16.3 EEPROM Control/Status Register (EEP_CONT_STAT)..............102 6.16.4 EEPROM Address Register (EEP_ADR) ....................103 6.16.5 EEPROM Data Register (EEP_DATA) ....................104 6.17 MII Management Interface Registers ......................
  • Page 10 6.21.2 Vender ID Register (VENDOR_ID) ...................... 141 6.21.3 User RAM (USER_RAM) ........................142 6.21.4 Process Data RAM (DATA_RAM) ....................... 143 6.22 Reset Circuit ..............................143 Ethernet PHY Function ..........................145 Features ................................145 Special Functions ............................145 7.2.1 Low Latency Function ........................... 145 7.2.2 Quick Auto-Negotiation Function ......................
  • Page 11 7.4.23 Register 30 - Interrupt Factor Mask Register ..................176 7.4.24 Register 31 - PHY Special Control/Status Register ................177 Ethernet PHY Function Setting Register ......................178 7.5.1 List of Registers ............................. 178 7.5.2 Ethernet PHY Operation Mode Control Register (PHYMD) ..............179 7.5.3 Ethernet PHY Power-Up Status Register (PHYPUS) ................
  • Page 12 Contents of Figures Figure 3.1 Memory Map (All) ..........................41 Figure 3.2 Memory Map (APB Peripheral Registers Area) ................. 42 Figure 3.3 Memory Map (External Memory Area) ....................43 Figure 3.4 Memory Map (CC-Link Master Area) ....................43 Figure 3.5 External MCU Interface Area ......................
  • Page 13 Contents of Tables Table 1.1 Overview of R-IN32M3-EC ........................2 Table 2.1 Meanings of the Items in the List of Pins ....................7 Table 2.2 Meanings of the Symbols and Abbreviations in the List of Pins .............. 7 Table 4.1 List of Interrupts .............................
  • Page 14 These requirements are not necessarily met by traditional methods such as hard-wired Ethernet processors or dedicated high-speed CPUs. Renesas R-IN32M3-EC of large-scale integrated circuits (LSI) are specifically tailored to meet the demands of industrial Ethernet applications. Key features include: •...
  • Page 15 R-IN32M3-EC User’s Manual 1. Overview Overview Table 1.1 Overview of R-IN32M3-EC (1/2) Product Item R-IN32M3-EC CPU cores Arm Cortex-M3 32-bit RISC CPU + Real-Time OS Accelerator (Hardware Real-Time OS, HW-RTOS) Operating frequency 100 MHz ® Instruction set Thumb -2 instruction Arm v7-M architecture Instruction RAM 768 Kbytes (RAM with ECC)
  • Page 16 R-IN32M3-EC User’s Manual 1. Overview (2/2) Product R-IN32M3-EC Item Internal peripheral circuit Watchdog timer - 1 channel - Software-triggered start mode - Selectable operations in response to errors: - Generation of a non-maskable interrupt (NMIZ) - Generation of a reset Asynchronous serial interface - 2 channels - Full duplex...
  • Page 17 R-IN32M3-EC User’s Manual 1. Overview Internal Block Diagram Timer Array UART × 2ch I2C × 2ch CAN × 2ch CSI × 2ch R18UZ0003EJ0501 Page 4 of 224 Jan. 12, 2021...
  • Page 18 R-IN32M3-EC User’s Manual 1. Overview Pin Assignments (Top View) R18UZ0003EJ0501 Page 5 of 224 Jan. 12, 2021...
  • Page 19 R-IN32M3-EC User’s Manual 1. Overview Base Addresses of the System Registers Area The addresses of registers given in the subsequent sections are relative to the base addresses. In access to the registers via the external MCU interface, the base address is D_0000H. In access by the internal CPU or DMA controller, the base address is 4001_0000H.
  • Page 20 Level after reset indicates the pin state directly after the transition to RSTOUTZ = high. For details on the reset specifications, see the R-IN32M3 Series User’s Manual (Peripheral Modules). Table 2.2 Meanings of the Symbols and Abbreviations in the List of Pins...
  • Page 21 R-IN32M3-EC User’s Manual 2. Pin Functions List of Pins 2.1.1 Ethernet Pins (1) Media Interface Pins Level during & after Pin Name Function Active Reset P0_RX_P PHY0 receive data input (+) P0_RX_N PHY0 receive data input (-) P1_RX_P PHY1 receive data input (+) P1_RX_N PHY1 receive data input (-) P0_TX_P...
  • Page 22 R-IN32M3-EC User’s Manual 2. Pin Functions (2) Other Pins Shared Level during & Pin Name Function Port Active after Reset P0LINKLEDZ On-chip PHY0 link status LED output Hi-Z P1LINKLEDZ On-chip PHY1 link status LED output ETHSWSECOUT EtherSwitch event output per second High P0DUPLEXLEDZ On-chip PHY0 half-duplex transfer status LED...
  • Page 23 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.2 EtherCAT Slave Controller Pins Shared Level during & after Pin Name Function Port Active Reset CATLEDRUN EtherCAT RUN LED output High Hi-Z CATIRQ EtherCAT IRQ output High CATLEDSTER EtherCAT dual-color state LED output High CATLEDERR EtherCAT error LED output...
  • Page 24 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.3 External Memory Interface Pins Shared Level during Level after Pin Name Function Shared Pin Port Active Reset Reset BUSCLK Bus clock output Clock output CSZ0 Chip select signal output HCSZ Hi-Z (High) High CSZ1 HPGCSZ Hi-Z (High)
  • Page 25 R-IN32M3-EC User’s Manual 2. Pin Functions Remark: Pins of the external memory interface pins other than BUSCLK are input pins while the internal reset signal (HRESETZ) is at its active level. Notes 1. While the synchronous burst access memory controller is in use, these signals are multiplexed with the address signals if the ADMUXMODE pin is driven high.
  • Page 26 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.4 External MCU Interface Pins Shared Level during & after Pin Name Function Shared Pin Port Active Reset HBUSCLK Bus clock input for host INTPZ11 Hi-Z (High) HCSZ Chip select signal input CSZ0 HPGCSZ Page POM mode chip CSZ1 select input...
  • Page 27 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.5 Port Pins and Real-Time Port Pins The ports and pins are configured as 12 sets of 8-bit ports. They are accessible in 32-bit units by grouping sets of 4 ports; i.e. ports 0 to 3, ports 4 to 7, and real-time ports 0 to 3. (1/4) Level during &...
  • Page 28 R-IN32M3-EC User’s Manual 2. Pin Functions (2/4) Level during & after Name Mode 1 Mode 2 Mode 3 Mode 4 Reset RXD1 Hi-Z (high) TXD1 DMAREQZ1 CCS_MON1 DMAACKZ1 CCS_MON2 DMATCZ1 CCS_MON3 CSISCK1 INTPZ22 CCM_IRLZ CSISI1 INTPZ23 CCS_FUSEZ CSISO1 INTPZ24 CCM_MSTZ A1/MA0 WAITZ HWAITZ...
  • Page 29 R-IN32M3-EC User’s Manual 2. Pin Functions (3/4) Level during & after Name Mode 1 Mode 2 Mode 3 Mode 4 Reset SCL0 Hi-Z SDA0 RTDMAREQZ CCM_MDIN0 RTDMAACKZ CCM_MDIN1 RTDMATCZ CCM_MDIN2 DMAREQZ0 CCM_MDIN3 DMAACKZ0 DMATCZ0 CSICS00 P0DUPLEXLEDZ CCS_STATION_NO_0 / CCM_SNIN0 CSICS01 CCS_STATION_NO_1 / CCM_SNIN1 CSICS10...
  • Page 30 R-IN32M3-EC User’s Manual 2. Pin Functions RP0x to RP3x function as real-time ports which can transfer data via a dedicated DMA controller. They are able to input and output data in 32-bit units in synchronization with the DMA transfer trigger. (4/4) Level during &...
  • Page 31 Caution: The DMA interface pin is fixed to the specific channel of the DMA controller, and not assigned to any other DMA controller or channel. For details, see section 13, DMA Controllers, in the R-IN32M3 Series User's Manual: Peripheral Modules. R18UZ0003EJ0501 Page 18 of 224 Jan.
  • Page 32 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.8 External Interrupt Input Pins The chip has one non-maskable interrupt and 29 maskable interrupt input pins. Level during & after Pin Name Function Shared Port Active Reset NMIZ Non-maskable external interrupt input Hi-Z (High) INTPZ0-INTPZ5 External interrupt input P00-P05...
  • Page 33 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.13 Serial Interface Pins Level during & after Pin Name Function Shared Port Active Reset TXD0 UART0 serial data output Hi-Z RXD0 UART0 serial data input TXD1 UART1 serial data output Hi-Z (High) RXD1 UART1 serial data input CSISCK0 CSI0 serial clock I/O...
  • Page 34 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.14 CC-Link Pins (Intelligent Device Station) Shared Level during & after Pin Name Function Port Active Reset CCM_LINKERRZ Link error LED control output Hi-Z CCM_ERRZ Not used CCM_RUNZ Run LED control output CCM_MDIN0- Transfer rate setting input P62-P65 CCM_MDIN3 CCM_SNIN0-...
  • Page 35 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.15 CC-Link Pins (Remote Device Station) Caution: To use a remote device station, it is necessary to connect a CCS_REFSTB (P10) pin to a port pin with the external interrupt function (INTPZ). Shared Level during & after Pin Name Function Port...
  • Page 36 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.16 System Pins Level during & after Pin Name Function Active Reset Clock input pins OSCTH = 1: Oscillator is in use. XT1 and XT2 are respectively connected to GND and oscillator. OSCTH = 0: Resonator is in use. XT1 and XT2 are connected to resonator RESETZ Reset input...
  • Page 37 Active Reset TMODE0-TMODE2 Test mode select pin Mode select signal Serial data input Serial data output TRSTZ Reset signal Clock signal (JTAG clock) TMC1 Renesas test pins TMC2 TEST1 TEST2 TEST3 TESTOUT5 R18UZ0003EJ0501 Page 24 of 224 Jan. 12, 2021...
  • Page 38 R-IN32M3-EC User’s Manual 2. Pin Functions 2.1.18 Operating Mode Setting Pins Level during & after Pin Name Function Active Reset BOOT1-BOOT0 Boot mode select 00: External memory boot 01: External serial flash ROM boot 10: External MPU boot 11: Instruction RAM boot (only available for debugging) MEMIFSEL External memory interface select 0: Slave memory interface...
  • Page 39 HIFSYNC = 0: Asynchronous SRAM interface mode HIFSYNC = 1: Synchronous SRAM interface mode For details, see section 11, External MCU Interface, in the R-IN32M3 Series User’s Manual (Peripheral Modules). 2. The external MCU interface HWRZ or HBENZ is selectable by the level on the HWRZSEL pin.
  • Page 40 R-IN32M3-EC User’s Manual 2. Pin Functions Pin States The initial state of the port functions after release from the reset state differs depending on the state of the operating mode setting pins. For the state of the operating mode setting pins in each boot mode and the supported combinations, see section 2.1.18, Operating Mode Setting Pins.
  • Page 41 R-IN32M3-EC User’s Manual 2. Pin Functions 2.2.1 Pin States when Booting is from External Memory External Memory Boot (BOOT1-0 = 00) Slave Memory Interface (MEMIFSEL = 0) Asynchronous SRAM Memory Controller (MEMCSEL = 0) Synchronous Burst Access Memory Controller (MEMCSEL = 1) Name 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1)
  • Page 42 R-IN32M3-EC User’s Manual 2. Pin Functions External Memory Boot (BOOT1-0 = 00) Slave Memory Interface (MEMIFSEL = 0) Asynchronous SRAM Memory Controller (MEMCSEL = 0) Synchronous Burst Access Memory Controller (MEMCSEL = 1) Name 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1) 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1) R18UZ0003EJ0501...
  • Page 43 R-IN32M3-EC User’s Manual 2. Pin Functions External Memory Boot (BOOT1-0 = 00) Slave Memory Interface (MEMIFSEL = 0) Asynchronous SRAM Memory Controller (MEMCSEL = 0) Synchronous Burst Access Memory Controller (MEMCSEL = 1) Name 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1) 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1) RP00...
  • Page 44 R-IN32M3-EC User’s Manual 2. Pin Functions 2.2.2 Pin States when Booting is from External Serial Flash ROM Remarks 1. Asynchronous type: Asynchronous SRAM memory controller (MEMCSEL = 0) Synchronous type: Synchronous burst access memory controller (MEMCSEL = 1) 2. 16-bit: 16-bit bus width of the external memory interface (BUS32EN = 0) 32-bit: 32-bit bus width of the external memory interface (BUS32EN = 1) External Serial Flash ROM Boot (BOOT1-0 = 01) Slave Memory Interface (MEMIFSEL = 0)
  • Page 45 R-IN32M3-EC User’s Manual 2. Pin Functions External Serial Flash ROM Boot (BOOT1-0 = 01) Slave Memory Interface (MEMIFSEL = 0) External MCU Interface (MEMIFSEL = 1) Asynchronous Type Synchronous Type Asynchronous Type Synchronous type Pin Name 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit...
  • Page 46 R-IN32M3-EC User’s Manual 2. Pin Functions External Serial Flash ROM Boot (BOOT1-0 = 01) Slave Memory Interface (MEMIFSEL = 0) External MCU Interface (MEMIFSEL = 1) Asynchronous Type Synchronous Type Asynchronous Type Synchronous type Pin Name 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit 16-bit...
  • Page 47 R-IN32M3-EC User’s Manual 2. Pin Functions 2.2.3 Pin States when Booting is for External MCU External MCU Boot (BOOT1-0 = 10) External MCU Interface (MEMIFSEL = 1) Asynchronous SRAM memory controller Synchronous burst access memory controller (MEMCSEL = 0) (MEMCSEL = 1) Name 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1)
  • Page 48 R-IN32M3-EC User’s Manual 2. Pin Functions External MCU Boot (BOOT1-0 = 10) External MCU Interface (MEMIFSEL = 1) Asynchronous SRAM memory controller Synchronous burst access memory controller (MEMCSEL = 0) (MEMCSEL = 1) Name 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1) 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1) HWAITZ...
  • Page 49 R-IN32M3-EC User’s Manual 2. Pin Functions External MCU Boot (BOOT1-0 = 10) External MCU Interface (MEMIFSEL = 1) Asynchronous SRAM memory controller Synchronous burst access memory controller (MEMCSEL = 0) (MEMCSEL = 1) Name 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1) 16-bit (BUS32EN = 0) 32-bit (BUS32EN = 1) RP00...
  • Page 50 R-IN32M3-EC User’s Manual 2. Pin Functions Buffer Types and Handling of Unused Pins 2.3.1 Ethernet Pins (1) Media Interface Pins Recommended Connection Pin Name Interface when Not in Use P0_RX_P 3.3-V analog input buffer Open P0_RX_N P1_RX_P P1_RX_N P0_TX_P 3.3-V analog output buffer Open P0_TX_N P1_TX_P...
  • Page 51 Set these pins according to the 50kΩ pull-down operating mode JTAGSEL Note: The pin connection differs depending on the setting of the OSCTH pin. For details, see the R-IN32M3 Series User’s Manual (Board design edition). 2.3.5 Test Pins Required Connection when Not Pin Name...
  • Page 52 R-IN32M3-EC User’s Manual 2. Pin Functions 2.3.6 Port Pins Recommended connection Pin Name Interface when Not in Use P00-P07 I/O buffer (3.3 V) (6 mA) Connect to GND Programmable I/O buffer (3.3 V) (6 mA) Open Resistor select function (50kΩ pull-up or 50kΩ pull-down or less) P11-P17 Programmable I/O buffer (3.3 V) (6 mA) Resistor select function...
  • Page 53 R-IN32M3-EC User’s Manual 2. Pin Functions 2.3.7 Operation Mode Setting Pins Recommended Connection Pin Name Interface when not in Use BOOT0, BOOT1 Input buffer (3.3 V) Schmitt in Set these pins according to the MEMIFSEL operating mode BUS32EN HIFSYNC HWRZSEL MEMCSEL ADMUXMODE 2.3.8...
  • Page 54 Note: The addresses of the instruction RAM mirror area (768 Kbytes) where access actually occurs will change according to the selected boot mode. For details, see section 5.3, Memory MAP in Each Boot Mode, in the R-IN32M3 Series User’s Manual: Peripheral Modules. R18UZ0003EJ0501 Page 41 of 224 Jan.
  • Page 55 R-IN32M3-EC User’s Manual 3. Memory Maps 4007 FFFFH ETHER SWITCH control register area (64 Kbytes) 4007 0000H Reserved CAN1 area (128 Kbytes) 4004 0000H CAN0 area (128 Kbytes) 4002 0000H System register area (64 Kbytes) 4001 0000H Reserved Watchdog timer (16 bytes) 4000 0700H Reserved...
  • Page 56 R-IN32M3-EC User’s Manual 3. Memory Maps 1FFF FFFFH CSZ3 area (64 Mbytes) 1C00 0000H 1BFF FFFFH CSZ2 area Reserved 2008 0000H (64 Mbytes) 2007 FFFFH 1800 0000H Data RAM area 17FF FFFFH (512 Kbytes) 2000 0000H CSZ1 area 1FFF FFFFH (64 Mbytes) External memory area 1400 0000H...
  • Page 57 For details, see section 5.3, Memory MAP in Each Boot Mode, and section 4, Bus Architecture, in the R-IN32M3 Series User’s Manual: Peripheral Modules. BOOT1 BOOT0...
  • Page 58 R-IN32M3-EC User’s Manual 4. Exception Handling Exception Handling The R-IN32M3 uses the interrupt controller of Cortex-M3. Refer to the following URL of Arm for the exceptions handling operation of Cortex-M3. http://infocenter.arm.com/help/topic/com.arm.doc.set.cortexm/index.html Exceptions List Exception numbers 1 to 15 are system exceptions of the Cortex-M3 CPU. Interrupts from the internal hardware of the R-IN32M3 and external pins are assigned to exception number 16 and higher exception numbers Exception Exception Type...
  • Page 59 R-IN32M3-EC User’s Manual 4. Exception Handling List of Interrupts The interrupts below are the exceptions (interrupts) with exception numbers 16 and higher, which are assigned to the NVIC of the Cortex-M3 CPU. In the R-IN32M3, interrupts from the internal hardware and external pins are connected not only to the NVIC of the Cortex-M3 but also to the internal hardware real-time OS (HW-RTOS), trigger for starting the internal DMA controllers (common to both the general-purpose DMAC and real-time port DMAC), real-time ports, and timers.
  • Page 60 R-IN32M3-EC User’s Manual 4. Exception Handling Table 4.1 List of Interrupts (1/4) Connected to Excep- Real- tion Time Name Interrupt Source NVIC RTOS DMAC Port Timer      INTTAUJ2I0 Timer array TAUJ2 channel 0 interrupt   ...
  • Page 61 R-IN32M3-EC User’s Manual 4. Exception Handling (2/4) Connected to Excep- Real- tion Time Name Interrupt Source NVIC RTOS DMAC Port Timer      INTCATSOF EtherCAT SOF interrupt      INTCATEOF EtherCAT EOF interrupt  ...
  • Page 62 R-IN32M3-EC User’s Manual 4. Exception Handling (3/4) Connected to Excep- Real- tion Time Name Interrupt Source NVIC RTOS DMAC Port Timer      INTPZ20 INTPZ20 input      INTPZ21 INTPZ21 input    ...
  • Page 63 R-IN32M3-EC User’s Manual 4. Exception Handling (4/4) Connected to Excep- Real- tion Time Name Interrupt Source NVIC RTOS DMAC Port Timer  BRAMECCDED Buffer RAM 2-bit ECC error detection interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
  • Page 64 R-IN32M3-EC User’s Manual 5. Peripheral Modules Peripheral Modules For details of the following peripheral modules, refer to the R-IN32M3 Series User’s Manual (Peripheral Modules). Clock function/Reset function CPU/Internal RAM Bus structure Hardware real-time OS Gigabit Ethernet interface Asynchronous SRAM memory controller...
  • Page 65 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function EtherCAT Slave Controller Function Features The EtherCAT slave controller (ESC) uses the EtherCAT slave controller IP core made by Beckhoff Automation GmbH, Germany. The ESC processes EtherCAT communications and acts as the interface between the EtherCAT field bus and slave applications.
  • Page 66 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Configuration of EtherCAT Slave Controller EtherCAT peripheral circuit Giga-bit Ethernet Ether MAC switch Media I/F 10/100M port ０ buffer EtherCAT MACSEL ETHDRCTRL slave controller CATRESET RESET Media I/F 10/100M port 1 CATODDADD buffer CATEMMD interface...
  • Page 67 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Interrupt and I/O Signals Table 6.2 Interrupt Signals of EtherCAT Slave Controller Connected to Excep- Real- tion Time Interrupt Signal Function NVIC RTOS DMAC Port Timer     INTCATSYNC0 EtherCAT sync0 interrupt ...
  • Page 68 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Functional Overview Typical functions of EtherCAT slave controller (ESC) and supported functions by R-IN32M3-EC are shown below. Regarding the detailed specifications of EtherCAT and ESC, refer to the documentation (e.g. ETG.1000 EtherCAT Specification) provided by EtherCAT Technology Group (ETG) and the EtherCAT Slave Controller IP Core (v2.04) datasheet provided by Beckhoff Automation GmbH.
  • Page 69 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function (2/3) Features Functions Supported ✓ SyncManager Buffered mode ✓ Mailbox mode ✓ Interrupt and latch event generation when a buffer was completely and successfully written or read ✓ Repeating mailbox communication ✓ SyncManager deactivation by the PDI ✓...
  • Page 70 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function (3/3) Features Functions Supported ✓ LED signals RUN LED signal ✓ ERR LED signal ✓ STATE LED and STATE_RUN LED signal ✓ LINK/ACT LED signals Port error LED signal ✓ RUN/ERR LED override Process data interface Digital I/O (PDI)
  • Page 71 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function List of EtherCAT Registers (1) Peripheral Function Registers Note Register Name Symbol Bits Address EtherCAT PHY offset address setting CATOFFADD BASE + 0620H EtherCAT operation mode setting CATEMMD BASE + 0624H EtherCAT reset CATRESET BASE + 0628H (2) ESC Information Registers...
  • Page 72 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function (6) Application Layer Registers Register Name Symbol Bits Address AL control AL_CONTROL 400E 0120H AL status AL_STATUS 400E 0130H AL status code AL_STATUS_CODE 400E 0134H RUN LED override RUN_LED_OVERRIDE 400E 0138H ERR LED override ERR_LED_OVERRIDE 400E 0139H (7) PDI Registers...
  • Page 73 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function (11) SII EEPROM Interface Registers Register Name Symbol Bits Address EEPROM configuration EEP_CONF 400E 0500H EEPROM PDI access state EEP_STATE 400E 0501H EEPROM control/status EEP_CONT_STAT 400E 0502H EEPROM address EEP_ADR 400E 0504H EEPROM data EEP_DATA 400E 0508H...
  • Page 74 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function (14) SyncManager Registers (m = 0 to 7) Register Name Symbol Bits Address SyncManager physical start address m SMm.P_START_ADR 400E 0800H + 0008H*m SyncManager length m SMm.LEN 400E 0802H + 0008H*m SyncManager control m SMm.CONTROL 400E 0804H + 0008H*m...

  • Page 75: Table Of Contents

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function (15) Distributed Clocks Registers Register Name Symbol Bits Address DC – Receive Time Registers Receive time port 0 DC_RCV_TIME_PORT0 400E 0900H Receive time port 1 DC_RCV_TIME_PORT1 400E 0904H DC – Time Loop Control Unit Registers System time DC_SYS_TIME 400E 0910H...
  • Page 76 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function (16) ETC Registers Register Name Symbol Byte Address Product ID PRODUCT_ID 400E 0E00H Vender ID VENDOR_ID 400E 0E08H User RAM USER_RAM 400E 0F80H - 400E 0FFFH Process data RAM DATA_RAM 400E 1000H - 400E 2FFFH Cautions 1.
  • Page 77 (SYSPCMD). Refer to the system protect command register (SYSPCMD) for protection releasing procedure. In addition, the special sequence is not necessary for reading the value from this register. For details on the system protect command register (SYSPCMD), see the R-IN32M3 Series User’s Manual (Peripheral Modules). Address...
  • Page 78 (SYSPCMD). Refer to the system protect command register (SYSPCMD) for protection releasing procedure. In addition, the special sequence is not necessary for reading the value from this register. For details on the system protect command register (SYSPCMD), see the R-IN32M3 Series User’s Manual (Peripheral Modules). Address...
  • Page 79 (SYSPCMD) for protection releasing procedure. In addition, the special sequence is not necessary for reading the value from this register. For details on the system protect command register (SYSPCMD), see the R-IN32M3 Series User’s Manual (Peripheral Modules). 2. Control this register after securing the time to satisfy reset width to EtherPHY by software in case of resetting EtherCAT.
  • Page 80 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function ESC Information Register 6.7.1 Type Register (TYPE) TYPE indicates the type of the EtherCAT slave controller. Address Initial Value TYPE TYPE 400E 0000H ECAT Bit Position Bit Name Description 7 to 0 TYPE Type of the EtherCAT slave controller 6.7.2...
  • Page 81 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.7.3 Build Register (BUILD) BUILD indicates the build number of the EtherCAT slave controller. Address Initial Value BUILD BUILD 400E 0002H 0000H ECAT Bit Position Bit Name Description 15 to 0 BUILD Build number of the EtherCAT slave controller 6.7.4 FMMUs Supported Register (FMMU_NUM)
  • Page 82 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.7.6 RAM Size Register (RAM_SIZE) RAM_SIZE indicates the process data RAM size supported by the EtherCAT slave controller in Kbytes. Address Initial Value RAMSIZE RAM_SIZE 400E 0006H ECAT Bit Position Bit Name Description 7 to 0 RAMSIZE...
  • Page 83 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.7.8 ESC Features Supported Register (FEATURE) FEATURE indicates the features supported by the EtherCAT slave controller. Address Initial Value FEATURE 400E 0008H 01CCH ECAT Bit Position Bit Name Description FSCONFIG Fixed FMMU/SyncManager Configuration 0: Variable configuration 1: Fixed configuration EtherCAT Read/Write Command Support (BRW, APRW, FPRW)
  • Page 84 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Station Address Registers 6.8.1 Configured Station Address Register (STATION_ADR) STATION_ADR indicates the address used for node addressing. Address Initial Value NODADDR STATION_ADR 400E 0010H 0000H ECAT R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit Position Bit Name Description...
  • Page 85 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Write Protection Registers 6.9.1 Write Register Enable Register (WR_REG_ENABLE) WR_REG_ENABLE is used to release the write protection temporarily when the write register protection is enabled. Address Initial Value WR_REG_ 400E 0020H ENABLE ECAT Bit Position Bit Name...
  • Page 86 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.9.3 ESC Write Enable Register (ESC_WR_ENABLE) ESC_WR_ENABLE is used to release the write protection temporarily when the ESC write protection is enabled. Address Initial Value ESC_WR_ 400E 0030H ENABLE ECAT Bit Position Bit Name Description If the ESC write protection is enabled (1 is set to bit 0 in the ESC write protection register...
  • Page 87 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.10 Data Link Layer Registers 6.10.1 ESC Reset ECAT Register (ESC_RESET_ECAT) ESC_RESET_ECAT is used to reset the EtherCAT slave controller from ECAT (master) by software. Write: Address Initial Value ESC_RESET_ RESET_ECAT 400E 0040H ECAT ECAT Bit Position...
  • Page 88 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.10.2 ESC Reset PDI Register (ESC_RESET_PDI) ESC_RESET_PDI is used to reset the EtherCAT slave controller from PDI by software. Write: Address Initial Value ESC_RESET_ RESET_PDI 400E 0041H ECAT Bit Position Bit Name Description A reset is asserted after writing 0x52 (“R”), 0x45 (“E”), and 0x53 (“S”) to this register with 3 7 to 0...
  • Page 89 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.10.3 ESC DL Control Register (ESC_DL_CONTROL) ESC_DL_CONTROL is used to control loop and configure RX FIFO size and station alias in the EtherCAT slave controller. Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400E 0100H Initial Value ESC_DL_...
  • Page 90 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Bit Position Bit Name Description Forwarding Rule FWDRULE 0: EtherCAT frames are processed. Non-EtherCAT frames are forwarded without processing. 1: EtherCAT frames are processed. Non-EtherCAT frames are destroyed. The source MAC address is changed for every frame (SOURCE_MAC[1] is set to 1 (locally administered address)) regardless of the forwarding rule.
  • Page 91 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.10.5 ESC DL Status Register (ESC_DL_STATUS) ESC_DL_STATUS indicates the EtherCAT slave controller status. Address Initial Value ESC_DL_ 400E 0110H 0004H STATUS ECAT (ack) (ack) (ack) (ack) (ack) (ack) (ack) (ack) (ack) (ack) (ack) (ack) (ack)
  • Page 92 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Bit Position Bit Name Description Physical Link on Port 0 PHYP0 0: No link 1: Link detected Enhanced Link Detection ENHLINKD 0: Deactivated for all ports 1: Activated for at least one port Note: The value of bit 9 at 0x0000 in the EEPROM is set.
  • Page 93 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.11 Application Layer Registers 6.11.1 AL Control Register (AL_CONTROL) AL_CONTROL indicates the state transition of the device state machine according to the request from the master. In addition, this register acknowledges an error indication from the slave. Address Initial Value...
  • Page 94 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.11.2 AL Status Register (AL_STATUS) AL_STATUS indicates the slave application status. Address Initial Value AL_STATUS 400E 0130H 0001H ECAT R/W R/W R/W R/W R/W R/W Bit Position Bit Name Description Device Identification Status DEVICEID 0: Device Identification not valid 1: Device Identification loaded...
  • Page 95 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.11.4 RUN LED Override Register (RUN_LED_OVERRIDE) RUN_LED_OVERRIDE is used to override RUN LED control. Address Initial Value RUN_LED_ LEDCODE 400E 0138H OVERRIDE ECAT Bit Position Bit Name Description Override Enable OVERRIDEEN 0: Override is disabled 1: Override is enabled 3 to 0 LEDCODE...
  • Page 96 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.11.5 ERR LED Override Register (ERR_LED_OVERRIDE) ERR_LED_OVERRIDE is used to override ERR LED control. Address Initial Value ERR_LED_ LEDCODE 400E 0139H OVERRIDE ECAT Bit Position Bit Name Description OVERRIDEEN Override Enable 0: Override is disabled 1: Override is enabled 3 to 0 LEDCODE...
  • Page 97 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.12 PDI Registers 6.12.1 PDI Control Register (PDI_CONTROL) PDI_CONTROL indicates the type of PDI. Address Initial Value PDI_CONTROL 400E 0140H ECAT Bit Position Bit Name Description 7 to 0 Process Data Interface This LSI indicates the value below.
  • Page 98 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.12.2 ESC Configuration Register (ESC_CONFIG) ESC_CONFIG indicates the configuration of EtherCAT slave controller. Address Initial Value Note ESC_CONFIG 400E 0141H ECAT Bit Position Bit Name Description Enhanced Link Detection of Port 3 (Port 3 is not available on this LSI.) ENLP3 0: Disabled (if bit 9 at address 0 in the EEPROM is 0) 1: Enabled...
  • Page 99 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.12.3 PDI Configuration Register (PDI_CONFIG) PDI_CONFIG indicates the PDI configuration. Address Initial Value ONCHIPBUS ONCHIPBUSCLK PDI_CONFIG 400E 0150H ECAT Bit Position Bit Name Description These bits indicate the type of on-chip bus. These bits always indicate 010 in this LSI. 7 to 5 ONCHIPBUS ONCHIPBUSCLK These bits indicate the on-chip bus clock.
  • Page 100 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.12.4 SYNC/LATCH PDI Configuration Register (SYNC_LATCH_CONFIG) SYNC_LATCH_CONFIG indicates the settings of SYNC output and LATCH input. Address Initial Value SYNC_LATCH_ Note 1 400E 0151H CONFIG ECAT Bit Position Bit Name Description SYNC1MAP SYNC1 Mapped to Bit 3 in AL Event Request Register (AL_EVENT_REQ: 0x0220) This bit always indicates 1 (enabled) in this LSI.
  • Page 101 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.12.5 Extended PDI Configuration Register (EXT_PDI_CONFIG) EXT_PDI_CONFIG indicates the configuration of extended PDI. Address Initial Value EXT_PDI_ 400E 0152H CONFIG ECAT Bit Position Bit Name Description These bits indicate the data bus width of PDI. 1, 0 DATABUSWID These bits always indicate 0 (4 bytes) in This LSI.
  • Page 102 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.13 Interrupts Registers 6.13.1 ECAT Event Mask Register (ECAT_EVENT_MASK) The ECAT event request (ECAT interrupt) is used to transmit the slave event to EtherCAT master. This register is used to set mask to each event of ECAT event request register (ECAT_EVENT_REQ: 0x0210). This register and ECAT event request register are ANDed and it is used as an interrupt.
  • Page 103 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.13.3 ECAT Event Request Register (ECAT_EVENT_REQ) ECAT_EVENT_REQ indicates events of ECAT event request (ECAT interrupt). Address Initial Value ECAT_EVENT_ 400E 0210H 0000H ECAT Bit Position Bit Name Description Mirror Value of SyncManager7 Status SMSTA7 0: No Sync Channel 7 event 1: Sync Channel 7 event pending...
  • Page 104 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Bit Position Bit Name Description DCLATCH DC Latch Event 0: No change on DC latch inputs 1: At least one change on DC latch inputs This bit is cleared by reading the DC latch event times from ECAT for the ECAT controlled latch units, so that the latch 0/1 status register (DC_LATCH_STAT0/1: 0x09AE:0x09AF) indicates no event.
  • Page 105 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.13.4 AL Event Request Register (AL_EVENT_REQ) AL_EVENT_REQ indicates events of AL event request (PDI interrupt). Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400E 0220H Initial Value AL_EVENT_...
  • Page 106 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Bit Position Bit Name Description DC Latch Event DCLATCH 0: No change on DC latch inputs 1: At least one change on DC latch inputs This bit is cleared by reading the DC latch event times from PDI for the PDI controlled latch units, so that the latch 0/1 status register (DC_LATCH_STAT0/1: 0x09AE:0x09AF) indicates no event.
  • Page 107 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.14 Error Counters Registers 6.14.1 Rx Error Counter n Register (RX_ERR_COUNTn) RX_ERR_COUNTn counts the number of receive frame errors. Address Initial Value RX_ERR_ RXERRCNT INVFRMCNT 400E 0300H 0000H COUNTn + 0002H*n ECAT (clr) (clr) (clr)
  • Page 108 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.14.3 ECAT Processing Unit Error Counter Register (ECAT_PROC_ERR_COUNT) ECAT_PROC_ERR_COUNT counts the number of frame errors passing the ECAT processing unit. Address Initial Value ECAT_PROC_ EPUERRCNT 400E 030CH ERR_COUNT R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr)
  • Page 109 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.14.5 Lost Link Counter n Register (LOST_LINK_COUNTn) LOST_LINK_COUNTn counts the number of lost links at port n. Address Initial Value LOST_LINK_ 400E 0310H LOSTLINKCNT COUNTn + 0001H*n R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr)
  • Page 110 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.15 Watchdogs Registers 6.15.1 Watchdog Divider Register (WD_DIVIDE) WD_DIVIDE is used to set the divider ratio for 25 MHz as the basic watchdog increment. Address Initial Value WDDIV WD_DIVIDE 400E 0400H 09C2H ECAT Bit Position Bit Name...
  • Page 111 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.15.3 Watchdog Time Process Data Register (WDT_DATA) WDT_DATA is used to set the overflow time of process data watchdog. Address Initial Value WDTIMPD WDT_DATA 400E 0420H 03E8H ECAT Bit Position Bit Name Description 15 to 0 WDTIMPD...
  • Page 112 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.15.5 Watchdog Counter Process Data Register (WDC_DATA) WDC_DATA indicates the number of timeout counts of process data watchdog. Address Initial Value WDCNTPD WDC_DATA 400E 0442H R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr) R/W(clr) ECAT Bit Position...
  • Page 113 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.16 SII EEPROM Interface Registers EtherCAT controls the SII EEPROM interface if bit 0 in the EEPROM configuration register (EEP_CONF: 0x0500) is 0 and bit 0 in the EEPROM PDI access state register (EEP_PDI_ACCESS: 0x0501) is 0. Otherwise PDI controls the EEPROM interface.
  • Page 114 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.16.2 EEPROM PDI Access State Register (EEP_STATE) EEP_STATE is used to configure the EEPROM access from PDI. Address Initial Value EEP_STATE 400E 0501H ECAT R/(W) Bit Position Bit Name Description Specifies the access control to EEPROM. PDIACCEES 0: PDI releases the EEPROM access.
  • Page 115 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.16.3 EEPROM Control/Status Register (EEP_CONT_STAT) EEP_CONT_STAT is used to control the EEPROM access and indicate the status. Address Initial Value EEP_CONT_ 400E 0502H 0000H STAT R/(W) R/(W) R/(W) R/(W) ECAT R/(W) R/(W) R/(W) Bit Position Bit Name Description...
  • Page 116 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Remark: Write access depends on the assignment of the EEPROM interface (ECAT/PDI). Write access is generally blocked if the EEPROM interface is busy (bit 15 = 1). Notes 1. The error bits are cleared by writing “000” (or any valid command) to command bits 10 to 8. .
  • Page 117 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.16.5 EEPROM Data Register (EEP_DATA) EEP_DATA is used to set write data to the EEPROM or indicates read data from the EEPROM. This register can be written in one word and read in two words. Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400E 0508H...
  • Page 118 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.17 MII Management Interface Registers 6.17.1 MII Management Control/Status Register (MII_CONT_STAT) MII_CONT_STAT is used to control the MII management interface and to indicate the status. Address Initial Value MII_CONT_ PHYOFFSET 400E 0510H 0006H STAT R/(W)
  • Page 119 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Remark: Write access depends on the assignment of the management interface (ECAT/PDI). Write access is generally blocked if the management interface is busy (bit 15 in this register is 1). Note: The write enable bit 0 is self-cleared at the SOF of the next frame (or at the end of the PDI access), and command bits 9 and 8 are also self-cleared after the command is executed (after the busy ends).
  • Page 120 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.17.3 PHY Register Address Register (PHY_REG_ADR) PHY_REG_ADR is used to set the PHY register address. Address Initial Value PHY_REG_ PHYREGADDR 400E 0513H R/(W) R/(W) R/(W) R/(W) R/(W) ECAT R/(W) R/(W) R/(W) R/(W) R/(W) Bit Position Bit Name...
  • Page 121 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.17.5 MII Management ECAT Access State Register (MII_ECAT_ACS_STAT) MII_ECAT_ACS_STAT is used to set the access state of MII management interface. Address Initial Value MII_ECAT_ 400E 0516H ACS_STAT R/(W) ECAT Bit Position Bit Name Description Access to MII Management Interface ACSMII...
  • Page 122 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.17.6 MII Management PDI Access State Register (MII_PDI_ACS_STAT) MII_PDI_ACS_STAT is used to set the access state of MII management interface. Address Initial Value MII_PDI_ 400E 0517H ACS_STAT ECAT R/(W) Bit Position Bit Name Description Forced Change of PDI Access State (Change Bit 0 Forcibly) FORPDI...
  • Page 123 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.17.7 PHY Port Status n Register (PHY_STATUSn) PHY_STATUSn indicates the PHY port status for each port. Address Initial Value PHY_ 400E 0518H STATUSn + 0001H*n R/(W/clr) R/(W/clr) ECAT R/(W/clr) R/(W/clr) Bit Position Bit Name Description PHY Configuration Updated...
  • Page 124 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.18 FMMU Registers 6.18.1 FMMU Logical Start Address Register m (FMMUm.L_START_ADR) FMMUm.L_START_ADR is used to set the logical start address within the EtherCAT address space for FMMU. Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400E 0600H FMMUm.
  • Page 125 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.18.3 FMMU Logical Start Bit Register m (FMMUm.L_START_BIT) FMMUm.L_START_BIT is used to set the start bit in the logical start address for FMMU. Address Initial Value FMMUm. 400E 0606H + LSTABIT 0010H*m L_START_BIT ECAT Bit Position...
  • Page 126 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.18.5 FMMU Physical Start Address Register m (FMMUm.P_START_ADR) FMMUm.P_START_ADR is used to set the physical start address of the ESC that is mapped to the logical start address for FMMU. Address Initial Value FMMUm.
  • Page 127 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.18.7 FMMU Type Register m (FMMUm.TYPE) FMMUm.TYPE is used to set the FMMU access type. Address Initial Value FMMUm. 400E 060BH + 0010H*m TYPE ECAT Bit Position Bit Name Description Specifies the write access mapping. WRITE 0: Ignores the mapping for write accesses 1: Use the mapping for write accesses...
  • Page 128 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.19 SyncManager Registers 6.19.1 SyncManager Physical Start Address Register m (SMm.P_START_ADR) SMm.P_START_ADR is used to set the physical start address of area assigned to SyncManager. Address Initial Value SMm. SMSTAADDR 400E 0800H 0000H P_START_ADR + 0008H*m...
  • Page 129 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.19.3 SyncManager Control Register m (SMm.CONTROL) SMm.CONTROL is used to control the operation of SyncManager. Address Initial Value SMm. 400E 0804H + 0008H*m CONTROL R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) ECAT Bit Position Bit Name Description...
  • Page 130 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.19.4 SyncManager Status Register m (SMm.STATUS) SMm.STATUS indicates the status of SyncManager. Address Initial Value SMm. 400E 0805H + 0008H*m STATUS ECAT Bit Position Bit Name Description Indicates that the buffer is being written. WRBUF Indicates that the buffer is being read.
  • Page 131 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.19.5 SyncManager Activate Register m (SMm.ACT) SMm.ACT is used to activate the operation of SyncManager. Address Initial Value SMm. 400E 0806H + 0008H*m ECAT R(ack) R(ack) R(ack) R(ack) Bit Position Bit Name Description LATCHPDI Latch Event in PDI...
  • Page 132 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.19.6 SyncManager PDI Control Register m (SMm.PDI_CONT) SMm.PDI_CONT is used to control SyncManager from the PDI. Address Initial Value SMm. 400E 0807H + 0008H*m PDI_CONT ECAT Bit Position Bit Name Description Repeat Acknowledge REPEATACK If this bit is set to the same value as bit 1 (repeat request) in the SyncManager activate register (SMm.ACT: 0x0806+8*m), the PDI acknowledges the repeat request.

  • Page 133: Dc_Rcv_Time_Port0

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20 Distributed Clocks Registers 6.20.1 DC Receive Time Registers 6.20.1.1 Receive Time Port 0 Register (DC_RCV_TIME_PORT0) DC_RCV_TIME_PORT0 is used to latch receive time of the frame at all ports if this register is written to, and to indicate the receive time latched at port 0 if this register is read.

  • Page 134: Dc_Sys_Time

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.2 DC Time Loop Control Unit Registers 6.20.2.1 System Time Register (DC_SYS_TIME) DC_SYS_TIME indicates the local copy of the system time. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 0910H Initial Value DC_SYS_...

  • Page 135: Dc_Rcv_Time_Unit

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.2.2 Receive Time ECAT Processing Unit Register (DC_RCV_TIME_UNIT) DC_RCV_TIME_UNIT indicates received time of the frame latched at the EtherCAT processing unit. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 0918H Initial Value DC_RCV_...

  • Page 136: Dc_Sys_Time_Offset

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.2.3 System Time Offset Register (DC_SYS_TIME_OFFSET) DC_SYS_TIME_OFFSET is used to indicate difference (offset) between the local time and the system time. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 0920H DC_SYS_ Initial Value...

  • Page 137: Dc_Sys_Time_Diff

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.2.5 System Time Difference Register (DC_SYS_TIME_DIFF) DC_SYS_TIME_DIFF indicates the average difference between the local copy of system time and the received system time. Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400E 092CH Initial Value DC_SYS_...

  • Page 138: Dc_Speed_Count_Diff

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.2.7 Speed Counter Difference Register (DC_SPEED_COUNT_DIFF) DC_SPEED_COUNT_DIFF indicates the deviation between the local clock period and the clock period of reference clock. Address Initial Value DC_SPEED_ SPDCNTDIFF 400E 0932H 0000H COUNT_DIFF ECAT Bit Position Bit Name Description...

  • Page 139: Dc_Speed_Count_Fil_Depth

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.2.9 Speed Counter Filter Depth register (DC_SPEED_COUNT_FIL_DEPTH) DC_SPEED_COUNT_FIL_DEPTH is used to set the filter depth for averaging the clock period deviation. Address Initial Value DC_SPEED_ CLKPERDEP COUNT_FIL_ 400E 0935H DEPTH ECAT Bit Position Bit Name Description 3 to 0...

  • Page 140: Dc_Act

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.4 SYNC Output Unit Registers 6.20.4.1 Activation Register (DC_ACT) DC_ACT is used to activate the SYNC output unit. Address Initial Value DC_ACT 400E 0981H R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) ECAT R/(W) R/(W)

  • Page 141: Dc_Pulse_Len

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.4.2 Pulse Length of Sync Signals Register (DC_PULSE_LEN) DC_PULSE_LEN indicates the pulse length of Sync signals. Address Initial Value DC_PULSE_ PULSELEN 0000H 400E 0982H Note ECAT Bit Position Bit Name Description 15 to 0 PULSELEN These bits indicate the pulse length of Sync signals (in 10-ns units).

  • Page 142: Dc_Sync0_Stat

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.4.4 SYNC0 Status Register (DC_SYNC0_STAT) DC_SYNC0_STAT indicates the status of SYNC0 output. This register is only used in acknowledge mode. Address Initial Value DC_SYNC0_ 400E 098EH STAT ECAT R(ack) Bit Position Bit Name Description Indicates the SYNC0 state for acknowledge mode.

  • Page 143: Dc_Cyc_Start_Time

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.4.6 Start Time Cyclic Operation/Next SYNC0 Pulse Register (DC_CYC_START_TIME) DC_CYC_START_TIME sets the start time of cyclic operation when written, and indicates the system time of next SYNC0 pulse when read. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 0990H DC_CYC_ Initial Value...

  • Page 144: Dc_Next_Sync1_Pulse

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.4.7 Next SYNC1 Pulse Register (DC_NEXT_SYNC1_PULSE) DC_NEXT_SYNC1_PULSE indicates the system time of next SYNC1 pulse. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 0998H Initial Value NEXT_...

  • Page 145: Dc_Sync1_Cyc_Time

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.4.9 SYNC1 Cycle Time Register (DC_SYNC1_CYC_TIME) DC_SYNC1_CYC_TIME is used to set the time between SYNC1 pulse and SYNC0 pulse. Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400E 09A4H Initial Value DC_SYNC1_...

  • Page 146: Dc_Latch1_Cont

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.5.2 Latch1 Control Register (DC_LATCH1_CONT) DC_LATCH1_CONT is used to control the edge function of Latch1 input signal. Address Initial Value DC_LATCH1_ 400E 09A9H CONT R/(W) R/(W) ECAT R/(W) R/(W) Bit Position Bit Name Description NEGEDGE Indicates the function of Latch1 negative edge.

  • Page 147: Dc_Latch1_Time_Pos

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.5.4 Latch1 Status Register (DC_LATCH1_STAT) DC_LATCH1_STAT indicates the status of Latch1 input signal. Address Initial Value DC_LATCH1_ 400E 09AFH STAT ECAT Bit Position Bit Name Description PINSTATE Indicates the status of Latch1 input pin. EVENTNEG Indicates the event of Latch1 input negative edge.
  • Page 148 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.5.5 Latch0 Time Positive Edge Register (DC_LATCH0_TIME_POS) DC_LATCH0_TIME_POS indicates the system time at the positive edge of Latch0 input signal. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 09B0H Initial Value SYSTIME...
  • Page 149 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.5.6 Latch0 Time Negative Edge Register (DC_LATCH0_TIME_NEG) DC_LATCH0_TIME_NEG indicates the system time at the negative edge of Latch0 input signal. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 09B8H Initial Value SYSTIME...
  • Page 150 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.5.7 Latch1 Time Positive Edge Register (DC_LATCH1_TIME_POS) DC_LATCH1_TIME_POS indicates the system time at the positive edge of Latch1 input signal. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 09C0H Initial Value SYSTIME...
  • Page 151 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.5.8 Latch1 Time Negative Edge Register (DC_LATCH1_TIME_NEG) DC_LATCH1_TIME_NEG indicates the system time at the negative edge of Latch1 input signal. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 09C8H Initial Value SYSTIME...

  • Page 152: Dc_Ecat_Cng_Ev_Time

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.6 SyncManager Event Times Registers 6.20.6.1 EtherCAT Buffer Change Event Time Register (DC_ECAT_CNG_EV_TIME) DC_ECAT_CNG_EV_TIME indicates the local time of reception beginning of the frame which causes at least one SyncManager to assert an ECAT event (buffer exchange). Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400E 09F0H...

  • Page 153: Dc_Pdi_Cng_Ev_Time

    R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.20.6.3 PDI Buffer Change Event Time Register (DC_PDI_CNG_EV_TIME) DC_PDI_CNG_EV_TIME indicates the local time when at least one SyncManager asserts a PDI event (buffer exchange). Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400E 09FCH DC_PDI_ Initial Value...
  • Page 154 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.21 ETC Registers 6.21.1 Product ID Register (PRODUCT_ID) PRODUCT_ID indicates the product ID. Address 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 400E 0E00H Initial Value PRODUCT_...
  • Page 155 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.21.3 User RAM (USER_RAM) USER_RAM indicates the supported features dependent on the IP core configuration. The area is 128 bytes from 400E 0F80H to 400E 0FFFH. The value “1” of initial value means supported features. However, bits 7 to 0 indicate the number of bits defined in the user RAM, and the value in the R-IN32M3-EC is 33H.
  • Page 156 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function 6.21.4 Process Data RAM (DATA_RAM) DATA_RAM is used for process data and mailbox. The area is 8 Kbytes from 400E 1000H to 400E 2FFFH. The process data RAM is only accessible when the EEPROM was correctly loaded (when bit 0 in the ESC DL status register (ESC_DL_STATUS: 0x0110) is 1).
  • Page 157 R-IN32M3-EC User’s Manual 6. EtherCAT Slave Controller Function Reset request by ECAT/PDI (0x0040/0x0041) ESC reset output Keep >=100us CATRESET register CATRST bit (ESC reset input) Around 1ms Both ESC reset and 0x0110.0 PHY reset are related. (EEPROM loaded) PHY reset pulse width restriction must be Reset Completion PHYMD register...
  • Page 158 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function Ethernet PHY Function Features The R-IN32M3-EC supports 10BASE-T, 100BASE-TX/FX, and integrated IEEE802.3 dual-port Ethernet physical layer (PHY). It is possible to connect twisted-pair (UTP) cable by the external pulse transformer or connect optical fiber by the optical transceiver.
  • Page 159 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.2.2 Quick Auto-Negotiation Function R-IN32M3-EC supports the quick auto-negotiation function which means completing auto negotiation in less time than the specific time of IEEE802.3 and link up. If the PHY is corresponding to the quick auto negotiation, auto negotiation can be complete in a shorter time than normal by reducing the timer time of the three elements described below among the auto negotiation state machine.
  • Page 160 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function ⚫ Link Fail Inhibit Timer The link fail inhibit timer is defined as the waiting time from signal loss or becomes abnormal to link down and it is usually 850 ms. These three timers can be set by setting bits 8 to 5 in register 18 (PHY_MODE[3:0] bits). When PHY_MODE[3] is 0, the value of PHY_MODE[1:0] cannot be reflected.
  • Page 161 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.2.3 Cable Diagnostic Function (TDR Function) The cable diagnostic function (TDR function) is a diagnostic function for detecting the type and location of abnormality when disconnection or short occurs in the Ethernet cable. This function outputs the pulse to the Ethernet cable and measures the time of pulse waveform reflected by the cable.
  • Page 162 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function The operation of TDR function is performed by using register 25 and register 26 as follows. Disable the auto-negotiation and auto-crossover and set to 100Base-Half Duplex at first, otherwise measuring cannot be performed correctly. Then, set the register with parameters relating to transmission pulse and pulse detection whether the TX line or RX line is measured.
  • Page 163 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function Start Send Pulse to TX Send Pulse to RX Parameter No.1 use Parameter No.3 use DIAGCNT=255 DIAGCNT=255 DIAGCNT<=42 56<=DIAGCNT<=88 Send Pulse to RX Send Pulse to TX Calculate distance Calculate distance Parameter No.1 use Parameter No.4 use Measure complete Measure complete...
  • Page 164 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.2.4 Fast Link-Loss Detection Function It is possible to generate the interrupt as soon as possible or bring down the link by monitoring the state of the communication when the communication is poor. Two functions with BER monitor and FEQ monitor are available. (1) BER Monitor The bit error rate (BER) monitor function can be used to measure the bit error of specific time, count the number of errors and notify.
  • Page 165 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function Power-Down Mode The hardware power-down mode, software power-down mode, and energy detection power-mode are available, and each of the power-down modes is described as follows. 7.3.1 Hardware Power-Down Mode The operation is shifted to hardware power-down mode by setting 1 to bit 2 (P0PHYEN) or bit 5（P1PHYEN) in the Ethernet PHY operation mode control register (PHYMD).
  • Page 166 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function MII Management Registers in Ethernet PHY The MII management registers are included in the Ethernet PHY. These registers specify various settings of the Ethernet PHY and capture the state of the Ethernet PHY. These registers can be accessed via the serial management interface from each MAC, by accessing the MIIM register of on-chip Ethernet MAC or the MII management interface register of EtherCAT slave controller.
  • Page 167 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function Symbols except R and W below bit names in each register section mean the following. : Self clearing after process completion : Latching low level, clear on read of register : Latching high level, clear on read of register NASR : Not initialized by software power-down mode R18UZ0003EJ0501 Page 154 of 224...
  • Page 168 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.1 Register 0 - Control Register Register 0 makes the basic settings of Ethernet PHY. Register Address (RESERVED) Initial Value 1000H Bit Position Bit Name Description Resets the Ethernet PHY. Settings of other bits in this register should not RESET be changed when resetting.
  • Page 169 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.2 Register 1 - Status Register Register 1 shows the status of Ethernet PHY. Register Address (RESERVED) Initial Value 7809H R/LH R/LL R/LH Bit Position Bit Name Description Enables/Disables 100BASE-T4 communication 100BASE-T4 0: Disabled 1: Enabled Enables/Disables 100BASE-TX full-duplex communication 100BASE-TX_...
  • Page 170 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.3 Registers 2, 3 - PHY Identifier Registers 2, 3 show the identification number of PHY in a total of 32 bits. Register Address PHY_ID_NUMBER Initial Value 0033H Bit Position Bit Name Description 3rd to 18th bits of OUI 15 to 0 PHY_ID_NUMBER...
  • Page 171 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.4 Register 4 - Auto-Negotiation Advertisement Register Register 4 indicates the information to be sent to the partner in auto-negotiation mode. Register Address SELECTOR_FIELD Initial Value 01E1H Bit Position Bit Name Description Support of Next Page Function NEXT_PAGE 0: Not supported 1: Supported...
  • Page 172 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.5 Register 5 - Auto-Negotiation Link Partner Ability (Base Page) Register Register 5 shows the base page of the information received from the partner when using auto negotiation. Register Address SELECTOR_FIELD Initial Value (Base Page) 0001H...
  • Page 173 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.6 Register 5 - Auto-Negotiation Link Partner Ability (Next Page) Register Register 5 shows the next page of the information received from the partner when using auto negotiation. Register Address MESSAGE_UNFORMATTED_CODE_FIELD Initial Value (Next Page) 0000H Bit Position...
  • Page 174 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.7 Register 6 - Auto-Negotiation Expansion Register Register 6 shows the information when using auto negotiation. Register Address (RESERVED) Initial Value 0004H R/LH R/LH Bit Position Bit Name Description Reserved (Write 0 and ignore reading) 15 to 5 (RESERVED) Shows whether the failure was detected in parallel detection function.
  • Page 175 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.8 Register 7 - Auto-Negotiation Next Page Transmit Register Register 7 shows the next page of the information to be transmitted to the partner when using auto negotiation. Register Address MESSAGE_UNFORMATTED_CODE_FIELD Initial Value 2001H Bit Position Bit Name...
  • Page 176 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.9 Register 16 - Silicon Revision Register Register 16 shows the silicon revision. Register Address (RESERVED) SILICON_REVISION (RESERVED) MR16 Initial Value 0040H Bit Position Bit Name Description Reserved (Write 0 and ignore reading) 15 to 10 (RESERVED) These bits show the silicon revision.
  • Page 177 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.10 Register 17 - Mode Control/Status Register Register 17 specifies the operating mode of Ethernet PHY. (1/2) Register Address MR17 Initial Value 0080H NASR Bit Position Bit Name Description Reserved (Write 0 and ignore reading) (RESERVED) Sets the 10BASE-T fast mode.
  • Page 178 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function (2/2) Bit Position Bit Name Description Enables/Disables the pattern generation for DCD measurement in test mode. DCD_PAT_GEN 0: Disabled 1: Enabled Reserved (Write 0 and ignore reading) (RESERVED) Shifts the operation to the link status forcibly. This bit is used only for testing. FORCE_GOOD_ 0: Normal operation LINK_STATUS...
  • Page 179 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.11 Register 18 - Special Mode Register Register 18 specifies the mode setting of Ethernet PHY. Register Address (RESERVED) PHY_MODE[3:0] PHY_ADD[4:0] MR18 Initial Value 00E0H NASR NASR NASR NASR NASR NASR NASR NASR NASR NASR Bit Position...
  • Page 180 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function Note 1. The timing of auto-negotiation can be changed in order to reduce the auto-negotiation time between 2 PHYs. It is possible to adjust the timing by changing the settings when link problem appears.
  • Page 181 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.14 Register 21 - Reserved Register Address (RESERVED) MR21 Initial Value 0000H Bit Position Bit Name Description Reserved (Write 0 and ignore reading) 15 to 0 (RESERVED) 7.4.15 Register 22 - Reserved Register Address (RESERVED) MR22 Initial Value...
  • Page 182 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.16 Register 23 - BER Counter Register Register 23 sets the BER counter function of Ethernet PHY and shows the BER results. Register Address BER_CNT_TRIG BER_WINDOW BER_COUNT MR23 Initial Value 5080H Bit Name Description Position Shows the quality status of the link.
  • Page 183 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.17 Register 24 - FEQ Monitor Register Register 24 sets the FEQ monitor function of Ethernet PHY and shows the FEQ results. Register Address FEQ_DELTA / FEQ_VAL MR24 Initial Value 0000H Bit Position Bit Name Description These bits set the amount of change in FEQ2 factor allowed for the value of the...
  • Page 184 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.18 Register 25 - Diagnostic Control/Status Register Register 25 sets the diagnostic function of Ethernet PHY and shows the results. Register Address ADC_MAX_VALUE / PW_DIAG MR25 Initial Value ADC_TRIGGER 0000H Bit Position Bit Name Description Reserved (Write 0 and ignore reading) (RESERVED)
  • Page 185 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.19 Register 26 - Diagnostic Counter Register Register 26 sets the diagnostic counter of Ethernet PHY and shows the results. MR26 Register Address CNT_WINDOW DIAGCNT Initial Value 0000H Bit Position Bit Name Description These bits set the time to mask as invalid detection result from the start of delivery 15 to 8 CNT_WINDOW...
  • Page 186 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.20 Register 27 - Special Control/Status Instruction Register Register 27 sets the PHY mode of Ethernet PHY and shows the results. Register Address (RESERVED) (RESERVED) (RESERVED) MR27 Initial Value 0001H NASR Bit Position Bit Name Description Reserved (Write 0 and ignore reading)
  • Page 187 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.21 Register 28 - Reserved Register 28 is used for testing. Please don’t read from or write to this register. Register Address (RESERVED) MR28 Initial Value 1400H Bit Position Bit Name Description Reserved 15 to 0 (RESERVED) R18UZ0003EJ0501...
  • Page 188 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.22 Register 29 - Interrupt Factor Register Register 29 indicates the source of interrupt when the interrupt output of Ethernet PHY is active. Bit 1 points to the cause of the interrupt. Interrupt output is cleared by reading. MR29 Register Address (RESERVED)
  • Page 189 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.23 Register 30 - Interrupt Factor Mask Register Register 30 enables/disables interrupt factors of Ethernet PHY. “0” is invalid (mask), while “1” is valid. MR30 Register Address (RESERVED) Initial Value 0000H Bit Position Bit Name Description Reserved (Write 0 and ignore reading)
  • Page 190 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.4.24 Register 31 - PHY Special Control/Status Register Register 31 does the configuration and status of the special features of Ethernet PHY. MR31 Register Address SPEED_ (RESERVED) (RESERVED) Initial Value INDICATION 0040H Bit Position Bit Name Description Reserved (Write 0 and ignore reading)
  • Page 191 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function Ethernet PHY Function Setting Register This register is used to change the operation that cannot be controlled by the MII management register of built-in Ethernet PHY without going through the serial management interface. 7.5.1 List of Registers Register Name...
  • Page 192 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.5.2 Ethernet PHY Operation Mode Control Register (PHYMD) PHYMD sets the operating mode of Ethernet PHY. It is a read/write accessible register in 32/16-bit units. Caution: This register can be written only in case of releasing protection by specific sequence using the system protect command register (SYSPCMD).
  • Page 193 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function 7.5.3 Ethernet PHY Power-Up Status Register (PHYPUS) PHYPUS is used to confirm the power-up state of the built-in Ethernet PHY. This register is readable only in 32 bits. When hardware power-down mode is released, bit1 and/or bit0 are cleared around 5.2ms later. Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE + 06A4H...
  • Page 194 R-IN32M3-EC User’s Manual 7. Ethernet PHY Function LED signal Output pins showing internal PHY status. External LED can be connected. Pin name Function Active P0LINKLEDZ Link Status P1LINKLEDZ 0: Linked 1: Unlinked － P0DUPLEXLEDZ Duplex Status P1DUPLEXLEDZ 0: Full duplex 1: Half duplex P0SPEED100LEDZ 100Mbps Link Status...
  • Page 195 R-IN32M3-EC User’s Manual 8. Port Function Port Function Features ⚫ Number of I/O ports: 96 ⚫ Can function alternately as the I/O pins of other peripheral functions. ⚫ Input or output can be specified by bit unit. Cautions 1. Switching from a signal for a peripheral module that is multiplexed with a port pin to port mode by changing the PMCn register setting might lead to a spike, depending on the state of the pin at the time.
  • Page 196 R-IN32M3-EC User’s Manual 8. Port Function Port Configuration The R-IN32M3-EC incorporates eight 3-state I/O ports and four real-time control ports. Input or output mode can be specified for ports in 1-bit units. The basic structure of ports is the 8-bit unit, but ports 0 to 3 can also be grouped to enable reading and writing in 32-bit units.
  • Page 197 R-IN32M3-EC User’s Manual 8. Port Function Alternate function Inactive Level Input alternate function 0 Alternate function Inactive Level Input alternate function 1 Alternate function Inactive Level Input alternate function 2 Alternate function Input alternate function 3 Inactive Level Alternate function 0 input/output attribute Inactive Level Alternate function 1...
  • Page 198 R-IN32M3-EC User’s Manual 8. Port Function List of Registers (1/6) Register Name Symbol Address Port register 0 (8 bits) 400A 3000H Port register 1 (8 bits) 400A 3001H Port register 2 (8 bits) 400A 3002H Port register 3 (8 bits) 400A 3003H Port register 4 (8 bits) 400A 3004H...
  • Page 199 R-IN32M3-EC User’s Manual 8. Port Function (2/6) Register Name Symbol Address Port mode control register 0 (8 bits) PMC0B 400A 3020H Port mode control register 1 (8 bits) PMC1B 400A 3021H Port mode control register 2 (8 bits) PMC2B 400A 3022H Port mode control register 3 (8 bits) PMC3B 400A 3023H...
  • Page 200 R-IN32M3-EC User’s Manual 8. Port Function (3/6) Register Name Symbol Address Port function control expansion register 0 (8 bits) PFCE0B 400A 3040H Port function control expansion register 1 (8 bits) PFCE1B 400A 3041H Port function control expansion register 2 (8 bits) PFCE2B 400A 3042H Port function control expansion register 3 (8 bits)
  • Page 201 R-IN32M3-EC User’s Manual 8. Port Function (4/6) Register Name Symbol Address RT port register 0 (8 bits) RP0B 400A 3400H RP1B 400A 3401H RT port register 1 (8 bits) RP2B 400A 3402H RT port register 2 (8 bits) RP3B 400A 3403H RT port register 3 (8 bits) RT port register 0 (16 bits) RP0H...
  • Page 202 R-IN32M3-EC User’s Manual 8. Port Function (5/6) Register Name Symbol Address RT port function control expansion register 0 (8 bits) RPFCE0B 400A 3440H RT port function control expansion register 1 (8 bits) RPFCE1B 400A 3441H RT port function control expansion register 2 (8 bits) RPFCE2B 400A 3442H RT port function control expansion register 3 (8 bits)
  • Page 203 R-IN32M3-EC User’s Manual 8. Port Function (6/6) Register Name Symbol Address Buffer function change register P1L DRCTLP1L 4001 0228H Buffer function change register P1H DRCTLP1H 4001 022CH Buffer function change register P3L DRCTLP3L 4001 0238H Buffer function change register P3H DRCTLP3H 4001 023CH Buffer function change register P4L...
  • Page 204 R-IN32M3-EC User’s Manual 8. Port Function 8.3.1 Port Registers (P, RP) The R-IN32M3-EC incorporates twelve 3-state I/O ports. Input or output can be specified in 1-bit units. The port registers are used for writing the output levels for output port pins. When read, the value of the given port register is read. The PIN and RPIN registers are used to read the levels on input pins.
  • Page 205 R-IN32M3-EC User’s Manual 8. Port Function Address 400A 3000H Initial Value 0000H Address 400A 3002H Initial Value 0000H Address 400A 3004H Initial Value 0000H Address 400A 3006H Initial Value 0000H Address RP0H RP17 RP16 RP15 RP14 RP13 RP12 RP11 RP10 RP07 RP06 RP05 RP04 RP03 RP02 RP01 RP00 400A 3400H Initial Value 0000H...
  • Page 206 R-IN32M3-EC User’s Manual 8. Port Function Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3000H Initial Value 0000 0000H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3004H...
  • Page 207 R-IN32M3-EC User’s Manual 8. Port Function 8.3.2 Port Mode Registers (PM, RPM) These registers are used to set a port to input or output mode. Initial Address Value PM0B PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 400A 3010H PM1B PM17 PM16 PM15...
  • Page 208 R-IN32M3-EC User’s Manual 8. Port Function Address PM0H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 400A 3010H Initial Value FFFFH Address PM2H PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 400A 3012H Initial Value FFFFH...
  • Page 209 R-IN32M3-EC User’s Manual 8. Port Function Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3010H Initial Value PM0W FFFF FFFFH R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3014H...
  • Page 210 R-IN32M3-EC User’s Manual 8. Port Function 8.3.3 Port Mode Control Register (PMC, RPMC) These registers are used to select whether to use a port as a port or for its alternate function. Initial Address Value PMC0B PMC07 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01...
  • Page 211 R-IN32M3-EC User’s Manual 8. Port Function Address PMC0H 400A 3020H Initial Value Note 1 0000H Address PMC2H 400A 3022H Initial Value Note 1 0000H Address PMC4H 400A 3024H Initial Value Note 1 0000H Address PMC6H 400A 3026H Initial Value Note 1 0000H Address RPMC0H...
  • Page 212 R-IN32M3-EC User’s Manual 8. Port Function Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3020H Initial Value PMC0W Note 1 0000 0000H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3024H...
  • Page 213 R-IN32M3-EC User’s Manual 8. Port Function 8.3.4 Port Function Control Registers (PFC, RPFC) These registers are used to specify which multiplexed function is to be used. These registers can be set in 1-bit units. Initial Address Value PFC0B PFC06 PFC05 PFC04 PFC03 PFC02...
  • Page 214 R-IN32M3-EC User’s Manual 8. Port Function Address PFC0H 400A 3030H Initial Value 0000H Address PFC2H 400A 3032H Initial Value Note 1 0000H Address PFC4H 400A 3034H Initial Value Note 1 0000H Address PFC6H 400A 3036H Initial Value Note 1 0000H Address RPFC RPFC...
  • Page 215 R-IN32M3-EC User’s Manual 8. Port Function Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3030H Initial Value 0 0 0 0 0 0 0 PFC0W Note 1 0000 0000H...
  • Page 216 R-IN32M3-EC User’s Manual 8. Port Function 8.3.5 Port Function Control Expansion Registers (PFCE, RPFCE) These registers are used to specify which multiplexed extended function is to be used. These registers can be set in 1-bit units. Initial Address Value PFCE0B PFCE07 PFCE06 PFCE05...
  • Page 217 R-IN32M3-EC User’s Manual 8. Port Function Address PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE0H 400A 3040H Initial Value 0000H Address PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE PFCE2H 400A 3042H Initial Value Note 1 0000H...
  • Page 218 R-IN32M3-EC User’s Manual 8. Port Function Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3040H Initial Value PFCE0W 0 0 0 0 0 0 0 Note 1 0000 0000H R/W R/W R/W R/W R/W R/W 0...
  • Page 219 R-IN32M3-EC User’s Manual 8. Port Function 8.3.6 Port Pin Input Registers (PIN, RPIN) These are read-only registers for reading the input level of port pins. Initial Address Value PIN0B PIN07 PIN06 PIN05 PIN04 PIN03 PIN02 PIN01 PIN00 400A 3050H Pin Level PIN1B PIN17 PIN16...
  • Page 220 R-IN32M3-EC User’s Manual 8. Port Function Address PIN0H 400A 3050H Initial Value Pin Level Address PIN2H 400A 3052H Initial Value Pin Level Address PIN4H 400A 3054H Initial Value Pin Level Address PIN6H 400A 3056H Initial Value Pin Level Address RPIN1 RPIN RPIN RPIN...
  • Page 221 R-IN32M3-EC User’s Manual 8. Port Function Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3050H Initial Value PIN0W Pin Level Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 400A 3054H Initial Value PIN4W...
  • Page 222 R-IN32M3-EC User’s Manual 8. Port Function List of Selectable Multiplexed Functions The table below lists the combinations of multiplexed functions that can be specified by using the port-related registers. (1) Ports (P00 to P77) (1/3) PMCmn = 1 (Control Mode) PMCmn = 0 (Port Mode) PFCEmn = 0 PFCEmn = 1...
  • Page 223 R-IN32M3-EC User’s Manual 8. Port Function (2/3) PMCmn = 1 (Control Mode) PMCmn = 0 (Port Mode) PFCEmn = 0 PFCEmn = 1 PFCmn = 0 PFCmn = 1 PFCmn = 0 PFCmn = 1 PMmn = 0 PMmn = 1 (Multiplexed (Multiplexed (Multiplexed...
  • Page 224 R-IN32M3-EC User’s Manual 8. Port Function (3/3) PMCmn = 1 (Control Mode) PMCmn = 0 (Port Mode) PFCEmn = 0 PFCEmn = 1 PFCmn = 0 PFCmn = 1 PFCmn = 0 PFCmn = 1 PMmn = 0 PMmn = 1 (Multiplexed (Multiplexed (Multiplexed...
  • Page 225 R-IN32M3-EC User’s Manual 8. Port Function (2) Real-time control ports (RP00 to RP37) PMCmn = 1 (Control Mode) PMCmn = 0 (Port Mode) RPFCEmn = 0 RPFCEmn = 1 PFCmn = 0 PFCmn = 1 PFCmn = 0 PFCmn = 1 PMmn = 0 PMmn = 1 (Multiplexed...
  • Page 226 R-IN32M3-EC User’s Manual 8. Port Function Buffer Switching Registers (DRCTL) For some port pins, the driving ability and the connection or disconnection of a pull-up or pull-down resistor is programmable. Set up the DRCTL registers during initialization after release from the reset state. After that, change the setting of a given DRCTL register only while the buffer functions for the corresponding pins are not in use.
  • Page 227 R-IN32M3-EC User’s Manual 8. Port Function 8.5.1 Port 1 Buffer Function Change Registers (DRCTLP1L, DRCTLP1H) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE + 0228H DRCTLP1L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial Value 0000 9959H...
  • Page 228 R-IN32M3-EC User’s Manual 8. Port Function 8.5.2 Port 3 Buffer Function Change Registers (DRCTLP3L, DRCTLP3H) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE + 0238H DRCTLP3L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial Value 0000 9999H...
  • Page 229 R-IN32M3-EC User’s Manual 8. Port Function 8.5.3 Port 4 Buffer Function Change Registers (DRCTLP4L, DRCTLP4H) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE + 0240H DRCTLP4L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial Value 0000 9999H...
  • Page 230 R-IN32M3-EC User’s Manual 8. Port Function 8.5.4 Port 5 Buffer Function Change Registers (DRCTLP5L, DRCTLP5H) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE + 0248H DRCTLP5L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial Value 0000 0599H...
  • Page 231 R-IN32M3-EC User’s Manual 8. Port Function 8.5.5 Real-Time Port 0 Buffer Function Change Registers (DRCTLRP0L, DRCTLRP0H) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE + 0260H DRCTLRP0L Initial Value...
  • Page 232 R-IN32M3-EC User’s Manual 8. Port Function 8.5.6 Real-Time Port 1 Buffer Function Change Registers (DRCTLRP1L, DRCTLRP1H) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE + 0268H DRCTLRP1L Initial Value...
  • Page 233 R-IN32M3-EC User’s Manual 8. Port Function 8.5.7 Real-Time Port 2 Buffer Function Change Registers (DRCTLRP2L, DRCTLRP2H) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE + 0270H DRCTLRP2L Initial Value...
  • Page 234 R-IN32M3-EC User’s Manual 8. Port Function 8.5.8 Real-Time Port 3 Buffer Function Change Registers (DRCTLRP3L, DRCTLRP3H) Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 BASE + 0278H DRCTLRP3L Initial Value...
  • Page 235 R-IN32M3-EC User’s Manual 8. Port Function Operation of Port Functions Operation of the ports differs depending on the I/O mode setting as described below. 8.6.1 Reading and Writing via I/O Ports (1) In Output Mode If a value is written to port register n (Pn or RPn), the value is written to that port's output latch (Pn or RPn). The value of the output latch is output from the pin.
  • Page 236 The state of the 32-bit port pins RP00 to RP37 can be updated in synchronization with an interrupt from an on-chip peripheral function. Use the RPTRGMD register to set trigger-synchronous port control mode in 1-bit units. To select the target trigger, use the RPTFR0 to RPTFR3 registers. For details, see the R-IN32M3 Series User’s Manual (Peripheral Modules). PORT RPx_DO (RTGPIO) RPxｘ...
  • Page 237 R-IN32M3-EC User’s Manual 9. Electrical Characteristics Electrical Characteristics For details on the electrical characteristics, refer to the R-IN32M3 Series Datasheet. R18UZ0003EJ0501 Page 224 of 224 Jan. 12, 2021...
  • Page 238 R-IN32M3-EC User’s Manual REVISION HISTORY R-IN32M3-EC User’s Manual REVISION HISTORY Rev. Date Description Page Summary 1.00 Feb. 8, 2013 First edition issued (Preliminary) 1.00 Apr. 03,2013 Overall Modification of English expressions Change the description of “CC-Link” Overall “CC-Link (Slave)” → “CC-Link (Remote device station)” Modification of the contents of 1.1 Introduction Standby mode deletion of Table1.1 Overview of R-IN32M3-EC Modification of the status of BUSCLK during the reset of 2.1.2 External...
  • Page 239 R-IN32M3-EC User’s Manual REVISION HISTORY Rev. Date Description Page Summary 2.01 Apr. 18,2014 Overall Modification of CC-Link Signals (Remote device station) Modification of the contents of ACKNOWLEDGE bit of 7.4.5 Register 5 - Auto-Negotiation Link Partner Ability (Base Page) Register 3.00 Jun.
  • Page 240 R-IN32M3-EC User’s Manual REVISION HISTORY Rev. Date Description Page Summary 4.00 Jan. 22, 2016 4.1 Exceptions List Abbreviations of reset pins, modified SYSRESET register, added 6.5 List of EtherCAT Registers, (7) PDI Registers Number of bits, modified 6.5 List of EtherCAT Registers, (16) ETC Registers Remark added 6.12.2 ESC Configuration Register (ESC_CONFIG) Initial value, and description on bit 0, modified...
  • Page 241 R-IN32M3-EC User’s Manual REVISION HISTORY Rev. Date Description Page Summary 4.01 Feb. 28, 2017 7.2.4 Fast Link-Loss Detection Function Explanation of error count method modified 7.3.1 Hardware Power-Down mode Minimum reset time added 7.4 MII Management Registers in Ethernet PHY Explanation about the symbols below bit name of registers added 154-176 7.4.1 Register 0 –...
  • Page 242 R-IN32M3-EC User’s Manual REVISION HISTORY [Memo] REVISION-5...
  • Page 243 R-IN32M3 Series User’s Manual: R-IN32M3-EC Publication Date: Rev.1.00 (Preliminary) Feb 08, 2013 Rev.5.01 Jan 12, 2021 Published by: Renesas Electronics Corporation...
  • Page 244 R-IN32M3 Series User’s Manual R-IN32M3-EC R18UZ0003EJ0501...

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