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2.
Items revised or added in previous versions
REVISION HISTORY
Rev.
Date
Page
1.01
Feb 03, 2009
-
1.10
Jul 15, 2009
-
3
4
5
18
20
21
29
40
44
44
46
48
49
49
50
50
51, 51
54
55
57
58
61
63
65
67
67
73, 76
78
86
92
93
104
104
107
117
119
122
123
134
136
148
151
169, 170 Figure 13.6 "I/O Ports (6/9)" and Figure 13.7 "I/O Ports (7/9)" note added
182
205
207
217
225
225
239
M16C/64A Group Hardware Manual
First Edition issued.
Watchdog Timer Reset Register → Watchdog Timer Refresh Register
Table 1.2 "Specifications for the 100-Pin Package (2/2)" partially modified
Table 1.3 "Product List" partially modified
Figure 1.2 "Marking Diagram (Top View)" partially modified
Figure 3.2 "Memory Map" 13800h → 13000h
Table 4.1 "SFR Information (1/16)" reset value in VCR1 modified
Table 4.2 "SFR Information (2/16)" reset value in VW1C modified and notes partially modified
Table 4.10 "SFR Information (10/16)" reset value in S11 modified
Figure 6.1 "Reset Circuit Block Diagram" list of SFRs modified
6.3 "Optional Function Select Area" partially added
6.3.1 "Optional Function Select Address 1 (OFS1)" partially modified
Table 6.6 "Pin Status When RESET Pin Level is Low" partially modified
Figure 6.3 "Reset Sequence" partially modified
6.4.2 "Hardware Reset" partially modified
Figure 6.4 "Reset Circuit Example" partially modified
6.4.3 "Power-On Reset Function" partially added
Figure 6.5 "Power-On Reset Circuit and Operation Example" partially modified
6.4.5 and 6.4.6 "Voltage Monitor 1, 2 Reset" partially modified
6.5.1 "Power Supply Rising Gradient" partially modified
Table 7.1 "Voltage Detector Specifications" partially modified
Table 7.2 "Registers" partially modified
7.2.1 "Voltage Detector 2 Flag Register (VCR1)" reset value modified
7.2.4 "Voltage Detector 1 Level Select Register (VD1LS)" partially modified
7.2.6 "Voltage Monitor 1 Control Register (VW1C)" partially modified
7.2.7 "Voltage Monitor 2 Control Register (VW2C)" partially modified
7.3 "Optional Function Select Area" partially added
7.3.1 "Optional Function Select Address 1 (OFS1)" partially modified
Figure 7.6 and Figure 7.8 "Voltage Monitor 1, 2 Interrupt/Reset Operation Example" partially modified
Table 8.1 "Clock Generator Specifications" partially modified
8.2.4 "Oscillation Stop Detection Register (CM2)" partially modified
Figure 8.3 "Relation between Main Clock and PLL Clock" partially modified
8.3.3 "125 kHz On-Chip Oscillator Clock (fOCO-S)" td (OCOS) → tsu(fOCO-S)
8.9.5 "PLL Frequency Synthesizer" deleted
8.9.5 "Starting PLL Clock Oscillation" added
9.2.2 "Flash Memory Control Register 2 (FMR2)" partially deleted
Table 9.6 "Resets and Interrupts to Exit Wait Mode and Conditions for Use" partially modified
Table 9.7 "Pin Status in Stop Mode" partially modified
9.4.2.1 "Slow Read Mode" partially modified
Figure 9.5 "Setting and Canceling Low Current Consumption Read Mode" partially modified
Table 11.1 "Bus Specifications" 0 to 2 software waits → 0 to 1 software waits
11.2.1 "Chip Select Control Register (CSR)" partially modified
Table 11.11 "Bits and Bus Cycles Related to Software Wait States (External Area)" note added
11.4.4 "Wait and RDY" partially deleted
13.4.2 "Priority Level of Peripheral Function I/O" partially deleted
Table 14.7 "Relocatable Vector Tables (2/2)" note partially modified
Figure 14.3 "Time Required for Executing Interrupt Sequence" note partially modified
Figure 14.12 "Procedure for Changing the Interrupt Generate Factor" partially modified
15.3 "Optional Function Select Area" partially added
15.3.1 "Optional Function Select Address 1 (OFS1)" partially modified
Table 16.7 "Timing at Which the DMAS Bit Changes State" partially modified
Description
Summary
C - 3
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