Renesas M16C/64A Series User Manual page 637

M16C/64A Group
(1) Low pulse is output automatically when a reception error occurs
While the CRXDEN bit is 0 (receive disabled), by setting the CABTEN bit to 1 (error low pulse output
enabled) followed by CRXDEN bit to 1 (receive enabled), an error low pulse is output for a receive error
automatically.
CEC
CRXDEN bit
CABTEN bit
CRERRFLG bit
IR bit
(2) Low pulse is output by a program when a reception error occurs
After setting the CRXDEN bit to 1 (receive enabled) and then setting the CABTEN bit to 1 if the
receiving data bit exceeds the tolerated range, a low pulse is output.
CEC
CRXDEN bit
CABTEN bit
CRERRFLG bit
IR bit
CRXDEN: Bit in the CECC3 register
CABTEN: Bit in the CECC4 register
CRERRFLG: Bit in the CECFLG register
IR: Bit in the CEC2IC register
The above assumes the following:
• The CFIL bit in the CECC2 register is 0 (filter disabled).
• The CRISEL2 bit in the CISEL register is 1 (receive error interrupt disabled).
• The CRISELS bit in the CISEL register is 0 (reception start bit interrupt disabled).
Figure 26.9 Low Pulse Output Timing in Receive Error
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Tolerated range error occurs
Becomes 1 when the low pulse ends
Tolerated range error occurs
26. Consumer Electronics Control (CEC) Function
Low pulse is generated
automatically
Set to 0 by acceptance of an
interrupt or by a program
Low pulse is generated when the CABTEN bit
becomes 1
Set to 1 in an interrupt routine
Set to 0 by acceptance of an interrupt
or by a program
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