Renesas M16C/64A Series User Manual page 462

M16C/64A Group
Frame starts
PMCi internal
input signal
DRFLG
PTHDFLG
PTD0FLG
PTD1FLG
REFLG
(EHOLD = 0)
REFLG
(EHOLD = 1)
The above assumes the following:
The HDEN bit in the PMCiCON0 register is 1 (header enabled)
i = 0, 1
REFLG, DRFLG, PTHDFLG, PTD0FLG, PTD1FLG: Bits in the PMCiSTS register
EHOLD: Bit in the PMC0CON0 register
Refer to EHOLD = 0 for PMC1.
Figure 22.7 Flag Operation Example
22.3.2.1 Header Detection (PMC0, PMC1)
While the HDEN bit in the PMCiCON0 register is 1 (header enabled), after data reception starts
(DRFLG flag is 1), when signal other than the header pattern is detected before the header is
detected, the following occur:
•
The REFLG bit in the PMCiSTS register becomes 1 (error occurs).
•
Bits PTD0FLG, PTD1FLG, and SDFLG in the PMCiSTS register remain unchanged even if the
detected signal is data 0, data 1, or special data.
•
Registers PMC0DAT0 to PMC0DAT5 remain unchanged.
When detecting the header in PMC0, set the SDEN bit in the PMC0CON0 register to 0 (special data
disabled).
22.3.2.2 Special Data Detection (PMC0)
When the SDEN bit in the PMC0CON0 register is 1 (special data enabled), special data can be
detected. When detecting special data, set the HDEN bit in the PMC0CON0 register to 0 (header
disabled).
22.3.2.3 Receive Data Buffer (PMC0)
There is a 6-byte (48-bit) buffer for storing received data. When the data exceeds 48 bits, the buffer is
sequentially overwritten from the first bit. Refer to 22.2.11 "PMC0 Receive Data Store Register i
(PMC0DATi) (i = 0 to 5)" and 22.2.10 "PMC0 Receive Bit Count Register (PMC0RBIT)".
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Receive error
Data 1
Header Data 0
Receive error is
detected
Frame ends
Data 0
Becomes 0 when next data
is detected
Becomes 0 when next data is detected
22. Remote Control Signal Receiver
Next frame starts
Header
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