Renesas M16C/64A Series User Manual page 537

M16C/64A Group
23.3.4.1 Clock Phase Setting Function
One of four combinations of transmit/receive clock phases and polarities can be selected using the
CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transmit/receive clock polarity and phase are the same for the master and slaves to be
used for communication.
Figure 23.33 shows the Transmit and Receive Timing in Master Mode (Internal Clock).
Clock output
(CKPOL = 0, CKPH = 0)
Clock output
(CKPOL = 1, CKPH = 0)
Clock output
(CKPOL = 0, CKPH = 1)
Clock output
(CKPOL = 1, CKPH = 1)
Data output timing
Data input timing
CKPOL: Bit in the UiC0 register
CKPH: Bit in the UiSMR3 register
Figure 23.33 Transmit and Receive Timing in Master Mode (Internal Clock)
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
High
Low
High
Low
High
Low
High
Low
High
D0 D1
Low
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
D2 D3 D4 D5 D6 D7
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