Renesas M16C/64A Series User Manual page 527

M16C/64A Group
1
(bus busy)
(See Note 1)
The above assumes the following:
XIN = 16 MHz, main clock divided by 1 (no division), UiBRG count source = f1
Note:
1. After a stop condition is generated, when generating the next start condition, after setting the STSPSEL bit in
the UiSMR4 register to 0 and waiting at least half a cycle of the SCL clock, then set the STAREQ bit to 1.
Technical update number: TN-16C-130A/EA
Figure 23.23 Register Setting Procedures for Condition Generation
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Start condition generation
BBS bit in the UiSMR
register is 1 ?
0 (bus free)
UiSMR4 ← 70h
UiMR ← 02h
UiBRG ← 0
UiSMR2 ← 03h
UiBRG ← IIC_BAUDRATE
UiSMR4 ← 71h
UiSMR4 ← 09h
End
Restart condition generation
UiSMR4 ← 02h
UiSMR4 ← 3Ah
End
Stop condition generation
UiSMR4 ← 04h
UiSMR4 ← 3Ch
End
23. Serial Interface UARTi (i = 0 to 2, 5 to 7)
Wait for bus release.
Set the STSPSEL bit to 0.
2
Select I C mode and internal clock .
Set the UiBRG register to 00h.
Executing this command requires at least half a cycle of
the SCL clock (62.5 ns).
Reset the UiBRG value to target bit rate.
Set the STAREQ bit to 1.
Set the STSPSEL bit to 1.
Set the RSTAREQ bit to 1.
Set the STSPSEL bit to 1.
Set the STPREQ bit to 1.
Set the STSPSEL bit to1.
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